Systems on a chip - Design and construction.

System level design model with re-use of system IP by: (Electronic resources)

A Platform-Centric Approach to System-on-Chip (SOC) Design by: (Language materials, printed)

System Level Design of Reconfigurable Systems-on-Chip by: (Language materials, printed)

Transaction Level Modeling with SystemC = TLM Concepts and Applications for Embedded Systems / by: (Language materials, printed)

ESL design and verification = a prescription for electronic system-level methodology / by: (Language materials, printed)

Networks on chip by: (Language materials, printed)

Design and test technology for dependable systems-on-chip by: (Electronic resources)

Multiprocessor system-on-chip = hardware design and tool integration / by: (Electronic resources)

On-chip instrumentation = design and debug for systems on chip / by: (Electronic resources)

Correct-by-construction approaches for SoC design by: (Electronic resources)

On-chip training NPU = algorithm, architecture and SoC design / by: (Electronic resources)

Towards heterogeneous multi-core systems-on-chip for edge machine learning = journey from single-core acceleration to multi-core heterogeneous systems / by: (Electronic resources)

Scalable multi-core architectures = design methodologies and tools / by: (Electronic resources)

Design concepts for a virtualizable embedded MPSoC architecture = enabling virtualization in embedded multi-processor systems / by: (Electronic resources)

System level design model with reuse of system IP by: (Language materials, printed)

Built-in-self-test and digital self-calibration for RF SoCs by: (Electronic resources)