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On-chip training NPU = algorithm, ar...

Han, Donghyeon.

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On-chip training NPU = algorithm, architecture and SoC design /

Record Type:	Electronic resources : Monograph/item
Title/Author:	On-chip training NPU/ by Donghyeon Han, Hoi-Jun Yoo.
Reminder of title:	algorithm, architecture and SoC design /
Author:	Han, Donghyeon.
other author:	Yoo, Hoi-Jun.
Published:	Cham :Springer Nature Switzerland : : 2023.,
Description:	xxiii, 237 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:	Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion.
Contained By:	Springer Nature eBook
Subject:	Systems on a chip - Design and construction. -
Online resource:	https://doi.org/10.1007/978-3-031-34237-0
ISBN:	9783031342370

On-chip training NPU = algorithm, architecture and SoC design /
Han, Donghyeon.

On-chip training NPUalgorithm, architecture and SoC design /[electronic resource] :by Donghyeon Han, Hoi-Jun Yoo. - Cham :Springer Nature Switzerland :2023. - xxiii, 237 p. :ill. (some col.), digital ;24 cm.

Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion.

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding.

ISBN: 9783031342370

Standard No.: 10.1007/978-3-031-34237-0doiSubjects--Topical Terms:

745351
Systems on a chip
--Design and construction.

LC Class. No.: TK7895.E42 / H36 2023

Dewey Class. No.: 621.3815

On-chip training NPU = algorithm, architecture and SoC design /
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300 $a xxiii, 237 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion.
520 $a Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding.
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700 1 $a Yoo, Hoi-Jun. $3 1531350
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