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Design-for-Test and Test Optimizatio...

Noia, Brandon.

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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs./
作者:	Noia, Brandon.
面頁冊數:	233 p.
附註:	Source: Dissertation Abstracts International, Volume: 75-08(E), Section: B.
Contained By:	Dissertation Abstracts International75-08B(E).
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3619071
ISBN:	9781303877537

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.
Noia, Brandon.

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. - 233 p.

Source: Dissertation Abstracts International, Volume: 75-08(E), Section: B.

Thesis (Ph.D.)--Duke University, 2014.

This item must not be sold to any third party vendors.

As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects have become the dominant contributor to circuit delay and a significant component of power consumption. In order to reduce the length of these interconnects, 3D integration and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry. 3D SICs not only have the potential to reduce average interconnect length and alleviate many of the problems caused by long global interconnects, but they can offer greater design flexibility over 2D ICs, significant reductions in power consumption and footprint in an era of mobile applications, increased on-chip data bandwidth through delay reduction, and improved heterogeneous integration.

ISBN: 9781303877537Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.
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500 $a Adviser: Krishnendu Chakrabarty.
502 $a Thesis (Ph.D.)--Duke University, 2014.
506 $a This item must not be sold to any third party vendors.
520 $a As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects have become the dominant contributor to circuit delay and a significant component of power consumption. In order to reduce the length of these interconnects, 3D integration and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry. 3D SICs not only have the potential to reduce average interconnect length and alleviate many of the problems caused by long global interconnects, but they can offer greater design flexibility over 2D ICs, significant reductions in power consumption and footprint in an era of mobile applications, increased on-chip data bandwidth through delay reduction, and improved heterogeneous integration.
520 $a Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex. Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a die stack, are a source of additional and unique defects not seen before in ICs. At the same time, testing these TSVs, especially before die stacking, is recognized as a major challenge. The testing of a 3D stack is constrained by limited test access, test pin availability, power, and thermal constraints. Therefore, efficient and optimized test architectures are needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively expensive.
520 $a Methods of testing TSVs prior to bonding continue to be a difficult problem due to test access and testability issues. Although some built-in self-test (BIST) techniques have been proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through TSV probing. This has the benefit of not needing large analog test components on the die, which is a significant drawback of many BIST architectures. Coupled with an optimization method described in this dissertation to create parallel test groups for TSVs, test time for pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.
520 $a The addition of boundary registers on functional TSV paths required for pre-bond probing results in an increase in delay on inter-die functional paths. This cost of test architecture insertion can be a significant drawback, especially considering that one benefit of 3D integration is that critical paths can be partitioned between dies to reduce their delay. This dissertation derives a retiming flow that is used to recover the additional delay added to TSV paths by test cell insertion.
520 $a Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary during 3D-SIC manufacturing. To reduce test cost, the test architecture and test scheduling for the stack must be optimized to reduce test time across all necessary test insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm dies, and soft dies, that give varying degrees of control over 2D test architectures on each die while optimizing the 3D test architecture. Integer linear programming models are developed to provide an optimal 3D test architecture and test schedule for the dies in the 3D stack considering any or all post-bond test insertions. Results show that the ILP models outperform other optimization methods across a range of 3D benchmark circuits.
520 $a In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs. The proposed techniques enable pre-bond TSV and structural test while maintaining a relatively low test cost. Future work will continue to enable testing of 3D SICs to move industry closer to realizing the true potential of 3D integration.
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773 0 $t Dissertation Abstracts International $g 75-08B(E).
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