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Advanced microarchitecture and circu...

Hsu, Steven K.

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Advanced microarchitecture and circuit design techniques for on-chip memories in CMOS technology.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Advanced microarchitecture and circuit design techniques for on-chip memories in CMOS technology./
作者:	Hsu, Steven K.
面頁冊數:	131 p.
附註:	Adviser: Shih-Lien Lu.
Contained By:	Dissertation Abstracts International67-10B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3236885
ISBN:	9780542910937

Advanced microarchitecture and circuit design techniques for on-chip memories in CMOS technology.
Hsu, Steven K.

Advanced microarchitecture and circuit design techniques for on-chip memories in CMOS technology. - 131 p.

Adviser: Shih-Lien Lu.

Thesis (Ph.D.)--Oregon State University, 2006.

These various design techniques show excellent promise in improving performance, power, area, and robustness of multi-ported register files in modern microprocessors.

ISBN: 9780542910937Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Advanced microarchitecture and circuit design techniques for on-chip memories in CMOS technology.
LDR:03588nam 2200301 a 45 001 973956
005 20110928
008 110928s2006 eng d
020 $a 9780542910937
035 $a (UMI)AAI3236885
035 $a AAI3236885
040 $a UMI $c UMI
100 1 $a Hsu, Steven K. $3 1297897
245 1 0 $a Advanced microarchitecture and circuit design techniques for on-chip memories in CMOS technology.
300 $a 131 p.
500 $a Adviser: Shih-Lien Lu.
500 $a Source: Dissertation Abstracts International, Volume: 67-10, Section: B, page: 5941.
502 $a Thesis (Ph.D.)--Oregon State University, 2006.
520 $a These various design techniques show excellent promise in improving performance, power, area, and robustness of multi-ported register files in modern microprocessors.
520 $a In modern on-chip memories, an increasing demand for higher performance, lower power, reduced area, and improved robustness creates a rising need for advanced microarchitecture and circuit design techniques. Particularly in large-signal multi-ported register files, these advanced design techniques include: (i) multi-banked arrays, (ii) multi-frequency arrays, (iii) multi-bit width gating, (iv) multi-latency cycle times, (v) multi-threshold devices, and (vi) multi-strength keepers. In modern microprocessors, register files are important ingredients, but the increasing number of register file read/write ports and entries can produce a bottleneck. This thesis discusses various new techniques, to address the challenges facing register file designers, and to satisfy microprocessor requirements.
520 $a The scalability of register files is a concern in modern microprocessors. As microprocessors become wider to exploit instruction level parallelism, this increases the amount of read/write ports. In turn this results in quadratic growth in register file area, decreasing frequency and increasing the power consumption. Multi-banked and multi-frequency register files reduce area and power consumption by relieving the read/write port congestion. Multi-bit width register files reduce active power during read/write operations by gating the clock/wordline. Pipelined register files improve frequency by reducing logic depth, but require multiple cycles for read/write operations. Multi-latency register files contain variable access cycle times, which are dependent on the physical locality of the data. This improves overall microprocessor performance and recovers lost instructions per cycle.
520 $a As instruction window size continues to expand in modern microprocessors, the resulting demand for additional register file entries requires increased use of wide-OR dynamic circuits. However, these circuits, primarily found in local/global bitlines, are susceptible to leakage noise. In a multi-threshold process, a self-reverse bias technique exploits the use of leaky low-V TH devices, reducing bitline leakage and improving robustness. This circuit topology improves bitline delay from reduced keeper contention. Downsized keepers improve bitline delay in low leakage conditions; stronger keepers improve bitline robustness in high leakage conditions. Utilizing this concept, register files with multi-strength keepers enable robust operation across a wide range of process, voltage, and temperature.
590 $a School code: 0172.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a Oregon State University. $3 625720
773 0 $t Dissertation Abstracts International $g 67-10B.
790 $a 0172
790 1 0 $a Lu, Shih-Lien, $e advisor
791 $a Ph.D.
792 $a 2006
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3236885