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Digital phase-locked loops for multi...

Kratyuk, Volodymyr.

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Digital phase-locked loops for multi-GHz clock generation.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Digital phase-locked loops for multi-GHz clock generation./
作者:	Kratyuk, Volodymyr.
面頁冊數:	90 p.
附註:	Advisers: Kartikeya Mayaram; Un-Ku Moon.
Contained By:	Dissertation Abstracts International68-01B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3247826

Digital phase-locked loops for multi-GHz clock generation.
Kratyuk, Volodymyr.

Digital phase-locked loops for multi-GHz clock generation. - 90 p.

Advisers: Kartikeya Mayaram; Un-Ku Moon.

Thesis (Ph.D.)--Oregon State University, 2007.

A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved performance similar to that of analog PLLs. However, there is an upper bound on the bandwidth of a DPLL and this limits its capability to track an input signal. The research described in this thesis is focused on new digital PLL architectures that overcome this bandwidth limitation in linear as well as in digital PLLs.Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Digital phase-locked loops for multi-GHz clock generation.
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245 1 0 $a Digital phase-locked loops for multi-GHz clock generation.
300 $a 90 p.
500 $a Advisers: Kartikeya Mayaram; Un-Ku Moon.
500 $a Source: Dissertation Abstracts International, Volume: 68-01, Section: B, page: 0504.
502 $a Thesis (Ph.D.)--Oregon State University, 2007.
520 $a A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise susceptible analog control for a voltage controlled oscillator (VCO) and the inherent noise immunity of digital circuits. Several recent digital PLL (DPLL) implementations have achieved performance similar to that of analog PLLs. However, there is an upper bound on the bandwidth of a DPLL and this limits its capability to track an input signal. The research described in this thesis is focused on new digital PLL architectures that overcome this bandwidth limitation in linear as well as in digital PLLs.
520 $a A systematic design procedure for a second-order digital phase-locked loop with a linear phase detector is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and a digital PLL. A new digital PLL architecture featuring a linear phase detector which eliminates the noise-bandwidth tradeoff is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and a low jitter. The measured results obtained from the prototype chip demonstrate a significant jitter improvement with the STDC.
520 $a A bang-bang digital PLL employing an adaptive tracking technique and a novel frequency acquisition scheme achieves a wide tracking range and fast frequency acquisition. The DPLL operates over a wide frequency range from 0.6GHz to 2GHz. The adaptive tracking mechanism detects PLL slewing by monitoring the output of the binary phase detector and corrects the VCO frequency to prevent loss of lock. The experimental results illustrate a tracking bandwidth improvement of 100%. As a result, this DPLL is suitable for applications employing spread-spectrum clocking. A fast frequency lock is achieved with a novel frequency detector which extracts the frequency error from the feedback divider in a PLL.
590 $a School code: 0172.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a Oregon State University. $3 625720
773 0 $t Dissertation Abstracts International $g 68-01B.
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790 1 0 $a Mayaram, Kartikeya, $e advisor
790 1 0 $a Moon, Un-Ku, $e advisor
791 $a Ph.D.
792 $a 2007
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