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Techniques for multicore power and t...

Donald, James.

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Techniques for multicore power and thermal management.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Techniques for multicore power and thermal management./
Author:	Donald, James.
Description:	126 p.
Notes:	Source: Dissertation Abstracts International, Volume: 68-03, Section: B, page: 1818.
Contained By:	Dissertation Abstracts International68-03B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3256594

Techniques for multicore power and thermal management.
Donald, James.

Techniques for multicore power and thermal management. - 126 p.

Source: Dissertation Abstracts International, Volume: 68-03, Section: B, page: 1818.

Thesis (Ph.D.)--Princeton University, 2007.

Power dissipation is now a primary limiting factor in the design of future microprocessors. As a consequence, effective control of on-chip temperature is continually becoming more costly. Most transistor failure mechanisms increase exponentially with temperature. While cooling mechanisms such as fans can modulate temperature, such solutions can be expensive, noisy, and have further reliability issues. Furthermore, due to non-uniform power density, non-uniform temperature profiles may create localized heating in the form of hotspots. In future process technologies, the power problem is exacerbated with relative increases in leakage power as opposed to dynamic power, and significant variation in leakage power.Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Techniques for multicore power and thermal management.
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035 $a (UMI)AAI3256594
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100 1 $a Donald, James. $3 552954
245 1 0 $a Techniques for multicore power and thermal management.
300 $a 126 p.
500 $a Source: Dissertation Abstracts International, Volume: 68-03, Section: B, page: 1818.
502 $a Thesis (Ph.D.)--Princeton University, 2007.
520 $a Power dissipation is now a primary limiting factor in the design of future microprocessors. As a consequence, effective control of on-chip temperature is continually becoming more costly. Most transistor failure mechanisms increase exponentially with temperature. While cooling mechanisms such as fans can modulate temperature, such solutions can be expensive, noisy, and have further reliability issues. Furthermore, due to non-uniform power density, non-uniform temperature profiles may create localized heating in the form of hotspots. In future process technologies, the power problem is exacerbated with relative increases in leakage power as opposed to dynamic power, and significant variation in leakage power.
520 $a This thesis explores policies for power and thermal management in modern processors. Such techniques can increase overall reliability while mitigating the cost of other cooling solutions. In particular, I approach power management with parameter variation from an analytical view, develop novel dynamic thermal management techniques for multithreaded processors, and explore a fairly exhaustive design space for thermal management in multicore processors. The overall contributions of this work are concepts, policies, analyses, and frameworks for management of power, temperature, variation, and performance on multicore processor platforms.
520 $a This thesis can be divided into two major parts. The first proposes a power management scheme for parallel applications. Rather than assuming predictable power characteristics, this study takes into account the natural variation in deep-submicron technologies. It is shown that while power variation can offset power/performance predictability, several benchmarks have convenient parallelism properties that allow a exible range of variation of as much as +/-98% of the target core design power. The second part of this thesis covers thermal management techniques for several processor design scenarios. I first propose an adaptive thermal management policy for single-core processors based on simultaneous multithreading. This adaptive technique based on controlling priorities between two threads is shown to increase performance for a thermally constrained core by on average 30%. I then further extend this to the multicore processor paradigm, whereby spatial locality allows for robust policies managing multiple hotspots across several cores. My final policy combines process migration with DVFS for a 2.6X performance improvement.
590 $a School code: 0181.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a Princeton University. $3 645579
773 0 $t Dissertation Abstracts International $g 68-03B.
790 $a 0181
791 $a Ph.D.
792 $a 2007
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3256594