東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Optimizing the Fast Fourier Transfor...

Chen, Long.

FindBook

Google Book

Amazon

博客來

Optimizing the Fast Fourier Transform on a many-core architecture.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Optimizing the Fast Fourier Transform on a many-core architecture./
作者:	Chen, Long.
面頁冊數:	66 p.
附註:	Adviser: Guang R. Gao.
Contained By:	Masters Abstracts International46-04.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1450065
ISBN:	9780549386919

Optimizing the Fast Fourier Transform on a many-core architecture.
Chen, Long.

Optimizing the Fast Fourier Transform on a many-core architecture. - 66 p.

Adviser: Guang R. Gao.

Thesis (M.S.)--University of Delaware, 2008.

The rapid revolution in microprocessor chip architecture due to multi-core and many-core technology is presenting an unprecedented challenge to the application developers as well as system software designers: how to exploit the performance potential due to such architectures effectively and efficiently?

ISBN: 9780549386919Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Optimizing the Fast Fourier Transform on a many-core architecture.
LDR:02737nam 2200301 a 45 001 954727
005 20110622
008 110622s2008 ||||||||||||||||| ||eng d
020 $a 9780549386919
035 $a (UMI)AAI1450065
035 $a AAI1450065
040 $a UMI $c UMI
100 1 $a Chen, Long. $3 1037955
245 1 0 $a Optimizing the Fast Fourier Transform on a many-core architecture.
300 $a 66 p.
500 $a Adviser: Guang R. Gao.
500 $a Source: Masters Abstracts International, Volume: 46-04, page: 2217.
502 $a Thesis (M.S.)--University of Delaware, 2008.
520 $a The rapid revolution in microprocessor chip architecture due to multi-core and many-core technology is presenting an unprecedented challenge to the application developers as well as system software designers: how to exploit the performance potential due to such architectures effectively and efficiently?
520 $a In this thesis, an in-depth study on optimizing the Fast Fourier Transform (FFT) on a many-core architecture is presented. The IBM Cyclops-64 (C64) chip architecture, the case study in this thesis, is a many-core chip architecture consisting of 160 thread units, associated memory banks and an interconnection network that connects them together in a shared memory organization.
520 $a The study presented in this thesis demonstrates how many-core architectures, like the C64, could be used to achieve a scalable high-performance implementation of FFT both in 1D and 2D cases. The thesis also analyzes the optimization challenges and opportunities, including problem decomposition, load balancing, work distribution, and data-reuse, together with the exploiting of the C64 architecture features such as the massive parallelism, explicit multi-level memory hierarchy and large register files.
520 $a The main contributions of this thesis include: (1) the development of scalable high-performance parallel FFT implementation on C64; (2) the study demonstrates that successful optimization for C64-like many-core architectures requires a careful analysis that can identify certain domain-specific features of a target application (e.g. FFT) and match them well with some key many-core architecture features; (3) the optimization procedure, assisted with the hand-tuned process, provides quantitative evidence on the importance of each optimization identified in (2) and valuable experience toward establishing an effective programming methodology for C64-like many-core architectures.
590 $a School code: 0060.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a University of Delaware. $b Department of Electrical and Computer Engineering. $3 1020805
773 0 $t Masters Abstracts International $g 46-04.
790 $a 0060
790 1 0 $a Gao, Guang R., $e advisor
791 $a M.S.
792 $a 2008
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1450065