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Design and modeling of high speed gl...

Chen, Guoqing.

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Design and modeling of high speed global on-chip interconnects.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Design and modeling of high speed global on-chip interconnects./
作者:	Chen, Guoqing.
面頁冊數:	269 p.
附註:	Adviser: Eby G. Friedman.
Contained By:	Dissertation Abstracts International68-05B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3263974
ISBN:	9780549021728

Design and modeling of high speed global on-chip interconnects.
Chen, Guoqing.

Design and modeling of high speed global on-chip interconnects. - 269 p.

Adviser: Eby G. Friedman.

Thesis (Ph.D.)--University of Rochester, 2007.

Interconnect has become a dominant factor in deep submicrometer (DSM) integrated circuits (ICs). With increasing levels of on-chip integration, more functional units are integrated onto a single die, such as a multi-core microprocessor and a system-on-chip. Global interconnect, which acts as a communication media among these functional units, plays an increasingly important role and can significantly limit the performance of advanced systems.

ISBN: 9780549021728Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Design and modeling of high speed global on-chip interconnects.
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245 1 0 $a Design and modeling of high speed global on-chip interconnects.
300 $a 269 p.
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500 $a Source: Dissertation Abstracts International, Volume: 68-05, Section: B, page: 3258.
502 $a Thesis (Ph.D.)--University of Rochester, 2007.
520 $a Interconnect has become a dominant factor in deep submicrometer (DSM) integrated circuits (ICs). With increasing levels of on-chip integration, more functional units are integrated onto a single die, such as a multi-core microprocessor and a system-on-chip. Global interconnect, which acts as a communication media among these functional units, plays an increasingly important role and can significantly limit the performance of advanced systems.
520 $a With decreasing on-chip clock periods, the timing characteristics of on-chip signals need to be determined and controlled more precisely. Accurate interconnect models are therefore critical to the IC design process. In this dissertation, two global inter connect models are presented. Closed-form expressions of the signal waveform are developed, which achieve good agreement with Spectre simulations.
520 $a During the interconnect design process, multiple design criteria are considered, such as delay, power, bandwidth, and noise. Repeaters are widely used in digital ICs to reduce interconnect delay and signal transition time with the penalty of additional power and area. A repeater insertion methodology is presented for achieving a tradeoff among different design criteria. Closed-form expressions for the number and size of the power optimal repeaters are developed.
520 $a With the scaling of CMOS technology, the requirements of different design criteria have become more stringent. It is increasingly difficult for conventional copper interconnect to satisfy these requirements. On-chip optical interconnect is shown to be a promising substitute for electrical interconnect in future advanced architectures. Critical lengths at which optical interconnect becomes advantageous are shown to be approximately one tenth of the chip edge length at the 22 nm technology node.
520 $a The focus of the IC design process in the DSM regime has shifted from logic optimization to interconnect optimization. The research presented in this dissertation provides several interconnect design and modeling methods to support this interconnect-centric design strategy.
590 $a School code: 0188.
650 4 $a Engineering, Electronics and Electrical. $3 626636
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710 2 $a University of Rochester. $3 515736
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790 1 0 $a Friedman, Eby G., $e advisor
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