語系:
繁體中文
English
說明(常見問題)
回圖書館首頁
手機版館藏查詢
登入
回首頁
切換:
標籤
|
MARC模式
|
ISBD
Power and thermal integrity analysis...
~
Li, Hang.
FindBook
Google Book
Amazon
博客來
Power and thermal integrity analysis and optimization for nanometer VLSI systems.
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Power and thermal integrity analysis and optimization for nanometer VLSI systems./
作者:
Li, Hang.
面頁冊數:
112 p.
附註:
Adviser: Sheldon Tan.
Contained By:
Dissertation Abstracts International68-06B.
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3270442
ISBN:
9780549089544
Power and thermal integrity analysis and optimization for nanometer VLSI systems.
Li, Hang.
Power and thermal integrity analysis and optimization for nanometer VLSI systems.
- 112 p.
Adviser: Sheldon Tan.
Thesis (Ph.D.)--University of California, Riverside, 2007.
With increasing integration density and soaring clock frequency in nowadays nanometer VLSI design, power and thermal integrity analysis has become the most important sign-off criteria for reliable, working silicon products. In this dissertation, we address two challenging problems relevant to increasing power and thermal integrity problems.
ISBN: 9780549089544Subjects--Topical Terms:
626636
Engineering, Electronics and Electrical.
Power and thermal integrity analysis and optimization for nanometer VLSI systems.
LDR
:03259nam 2200289 a 45
001
941960
005
20110519
008
110519s2007 ||||||||||||||||| ||eng d
020
$a
9780549089544
035
$a
(UMI)AAI3270442
035
$a
AAI3270442
040
$a
UMI
$c
UMI
100
1
$a
Li, Hang.
$3
898292
245
1 0
$a
Power and thermal integrity analysis and optimization for nanometer VLSI systems.
300
$a
112 p.
500
$a
Adviser: Sheldon Tan.
500
$a
Source: Dissertation Abstracts International, Volume: 68-06, Section: B, page: 4022.
502
$a
Thesis (Ph.D.)--University of California, Riverside, 2007.
520
$a
With increasing integration density and soaring clock frequency in nowadays nanometer VLSI design, power and thermal integrity analysis has become the most important sign-off criteria for reliable, working silicon products. In this dissertation, we address two challenging problems relevant to increasing power and thermal integrity problems.
520
$a
First, we develop a complete optimization framework for noise reduction in on-chip power delivery networks by adding decoupling capacitors (decap). Upon the in-depth analysis on previous algorithms, we propose two efficient optimization algorithms in budgeting decaps. Both approaches are based on time-domain adjoint network method in computing the sensitivities used for the search direction in the optimization process. The sequence linear programming (SLP) based algorithm provides high convergence rate and better optimization quality due to the individual sensitivity used from each violation node. The conjugate gradient (CG) based algorithm is fast in run-time speed by using the merged-adjoint network method and improved search step scheme, which significantly reduces the transient simulations for sensitivity computation. In the end, a novel partitioning scheme is proposed to make the algorithm scalable to handle large decap optimization problems. We show that this flow is not only capable of handling multi-millions node circuit, but also can improve the budget quality as compared to a flat optimization scheme. The flow can be readily adopted in the available floor-plan tool for decap insertion optimization.
520
$a
Second, we explore a new software-based temperature sensing solution used in dynamic thermal management for microprocessors. The method is realized by moment matching technique from frequency domain analysis, which is ideal for compact architecture level thermal models. Our approach is based on observation that the average power determines the temperature variation trend, moment matching method based on average powers can accurately predict the thermal curve over time by a closed-form function. The proposed method is much faster than the integration-based solution, and improves the run time drastically with marginal errors. The proposed method promises fast on-chip software thermal estimation and serves as a steppingstone for many thermal related optimization and regulations.
590
$a
School code: 0032.
650
4
$a
Engineering, Electronics and Electrical.
$3
626636
690
$a
0544
710
2
$a
University of California, Riverside.
$3
791122
773
0
$t
Dissertation Abstracts International
$g
68-06B.
790
$a
0032
790
1 0
$a
Tan, Sheldon,
$e
advisor
791
$a
Ph.D.
792
$a
2007
856
4 0
$u
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3270442
筆 0 讀者評論
館藏地:
全部
電子資源
出版年:
卷號:
館藏
1 筆 • 頁數 1 •
1
條碼號
典藏地名稱
館藏流通類別
資料類型
索書號
使用類型
借閱狀態
預約狀態
備註欄
附件
W9111332
電子資源
11.線上閱覽_V
電子書
EB W9111332
一般使用(Normal)
在架
0
1 筆 • 頁數 1 •
1
多媒體
評論
新增評論
分享你的心得
Export
取書館
處理中
...
變更密碼
登入