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Time and power optimization for hete...

Qiu, Meikang.

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Time and power optimization for heterogeneous parallel embedded systems.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Time and power optimization for heterogeneous parallel embedded systems./
作者:	Qiu, Meikang.
面頁冊數:	213 p.
附註:	Adviser: Edwin Sha.
Contained By:	Dissertation Abstracts International68-03B.
標題:	Computer Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3256506

Time and power optimization for heterogeneous parallel embedded systems.
Qiu, Meikang.

Time and power optimization for heterogeneous parallel embedded systems. - 213 p.

Adviser: Edwin Sha.

Thesis (Ph.D.)--The University of Texas at Dallas, 2007.

For heterogeneous parallel embedded systems, we exploit the time and power optimization in various aspects. In high-level architecture synthesis, we address high-level architecture synthesis for real-time Digital Signal Processing (DSP) using heterogeneous functional units (FUs). With more and more different types of FUs available, same type of operations can be processed by heterogeneous FUs with different costs, where the cost may relate to power, reliability, etc. Furthermore, some tasks may not have fixed execution time. Such tasks usually contain conditional instructions and/or operations that could have different execution times for different inputs. Therefore, for such special purpose architecture synthesis, an important problem is how to assign a proper function unit type to each operation of a DSP application and generate a schedule in such a way that we can minimize the total costs while satisfying timing constraints with guaranteed confidence probabilities. We propose several efficient algorithms to solve it. The experiments show that our algorithms can effectively reduce the total cost compared with the previous work.Subjects--Topical Terms:

626642
Computer Science.

Time and power optimization for heterogeneous parallel embedded systems.
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245 1 0 $a Time and power optimization for heterogeneous parallel embedded systems.
300 $a 213 p.
500 $a Adviser: Edwin Sha.
500 $a Source: Dissertation Abstracts International, Volume: 68-03, Section: B, page: 1735.
502 $a Thesis (Ph.D.)--The University of Texas at Dallas, 2007.
520 $a For heterogeneous parallel embedded systems, we exploit the time and power optimization in various aspects. In high-level architecture synthesis, we address high-level architecture synthesis for real-time Digital Signal Processing (DSP) using heterogeneous functional units (FUs). With more and more different types of FUs available, same type of operations can be processed by heterogeneous FUs with different costs, where the cost may relate to power, reliability, etc. Furthermore, some tasks may not have fixed execution time. Such tasks usually contain conditional instructions and/or operations that could have different execution times for different inputs. Therefore, for such special purpose architecture synthesis, an important problem is how to assign a proper function unit type to each operation of a DSP application and generate a schedule in such a way that we can minimize the total costs while satisfying timing constraints with guaranteed confidence probabilities. We propose several efficient algorithms to solve it. The experiments show that our algorithms can effectively reduce the total cost compared with the previous work.
520 $a Low power is becoming a critical design issue and performance metric in embedded system design. DSP processor has multiple FUs and can process several instructions simultaneously. While this multiple-FU architecture can be exploited to increase instruction-level parallelism and improve time performance, it causes more power consumption. To solve this problem, several techniques have been proposed. We combine Dynamic Voltage Scaling (DVS) and soft real-time to solve the Voltage Assignment with Probability (VAP) Problem. VAP problem involves finding a voltage level to be used for each node of an Probabilistic Date Flow Graph (PDFG) in uniprocessor and multiprocessor DSP systems. This work tremendously improves the state-of-the-art techniques. Another application is heterogeneous sensor network. We apply our efficient algorithms to dynamic adjust the working mode of sensors and achieved significant energy saving. Also, we design new rotation scheduling algorithms for real-time applications that produce schedules consuming minimal energy. Furthermore, we combine data mining and prefetching to reduce energy consumption. All these three techniques significantly reduce energy consumption.
520 $a Many high-performance DSP processors employ multi-bank on-chip memory to improve performance and energy consumption. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. However, making effective use of multi-bank memory remains difficult, considering the combined effect of performance and energy requirement. In this project, our focus is to study the assignment and scheduling problem that minimizes the total energy while satisfying performance requirements. Our approach has several major contributions: First, we study the combined effects of energy-saving and performance of memory in a systematic approach. Second, we exploit the energy saving of memory with memory type assignment. Third, data locality has been improved by using variable partition.
590 $a School code: 0382.
650 4 $a Computer Science. $3 626642
650 4 $a Engineering, Electronics and Electrical. $3 626636
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710 2 $a The University of Texas at Dallas. $3 1018411
773 0 $t Dissertation Abstracts International $g 68-03B.
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791 $a Ph.D.
792 $a 2007
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