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Design techniques for low-voltage an...

Chang, Dong-Young.

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Design techniques for low-voltage analog-to-digital converter.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Design techniques for low-voltage analog-to-digital converter./
作者:	Chang, Dong-Young.
面頁冊數:	89 p.
附註:	Adviser: Un-Ku Moon.
Contained By:	Dissertation Abstracts International64-02B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3080140

Design techniques for low-voltage analog-to-digital converter.
Chang, Dong-Young.

Design techniques for low-voltage analog-to-digital converter. - 89 p.

Adviser: Un-Ku Moon.

Thesis (Ph.D.)--Oregon State University, 2003.

Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal) which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which are not always scalable to very low voltage supplies as it could suffer from an unacceptable amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp (SO) technique which is fully compatible with low-voltage submicron CMOS processes but the operating speed limited due to slow transients from the opamp being switched off and on.Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Design techniques for low-voltage analog-to-digital converter.
LDR:03166nam 2200277 a 45 001 936177
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035 $a (UnM)AAI3080140
035 $a AAI3080140
040 $a UnM $c UnM
100 1 $a Chang, Dong-Young. $3 1259870
245 1 0 $a Design techniques for low-voltage analog-to-digital converter.
300 $a 89 p.
500 $a Adviser: Un-Ku Moon.
500 $a Source: Dissertation Abstracts International, Volume: 64-02, Section: B, page: 0865.
502 $a Thesis (Ph.D.)--Oregon State University, 2003.
520 $a Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal) which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which are not always scalable to very low voltage supplies as it could suffer from an unacceptable amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp (SO) technique which is fully compatible with low-voltage submicron CMOS processes but the operating speed limited due to slow transients from the opamp being switched off and on.
520 $a In this thesis, the <italic>Opamp-Reset Switching Technique</italic> (ORST) topology is proposed for low-voltage operation. Instead of opamps being turned on and off as in the switched-opamp technique, the sourcing amplifier is placed in the unity-gain reset configuration to provide reset level at the output. In this way, high-speed operation is possible, The technique is applied to two ADCs as examples of low-voltage design.
520 $a The first design is a 10-bit 25MSPS pipelined ADC using pseudo-differential structure. It is fabricated in a 0.35-μm CMOS process. It operates at 1.4V and consumes 21mW of total power. The second design is a two-stage algorithmic ADC with highly linear input sampling circuit. In addition to the low-voltage design techniques used in the pipelined ADC, radix-based digital calibration technique for multi-stage ADC is also proposed. The ADC uses a 0.18-μm CMOS technology. It operates at 0.9V supply with total power consumption of 9mW. Experimental results show that the proposed calibration technique reduces spurious free dynamic range from 47dB to 75dB and improves signal-to-noise and distortion ratio from 40dB to 55dB after calibration.
590 $a School code: 0172.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a Oregon State University. $3 625720
773 0 $t Dissertation Abstracts International $g 64-02B.
790 $a 0172
790 1 0 $a Moon, Un-Ku, $e advisor
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3080140