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Noise analysis and optimization in m...

Heydari, Payam.

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Noise analysis and optimization in mixed-signal VLSI circuits.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Noise analysis and optimization in mixed-signal VLSI circuits./
作者:	Heydari, Payam.
面頁冊數:	142 p.
附註:	Adviser: Massoud Pedram.
Contained By:	Dissertation Abstracts International63-12B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3073790
ISBN:	0493938958

Noise analysis and optimization in mixed-signal VLSI circuits.
Heydari, Payam.

Noise analysis and optimization in mixed-signal VLSI circuits. - 142 p.

Adviser: Massoud Pedram.

Thesis (Ph.D.)--University of Southern California, 2002.

The new methods and formulations presented in this thesis represent efficient and accurate techniques for the noise analysis and optimization in the mixed-signal VLSI circuits.

ISBN: 0493938958Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Noise analysis and optimization in mixed-signal VLSI circuits.
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245 1 0 $a Noise analysis and optimization in mixed-signal VLSI circuits.
300 $a 142 p.
500 $a Adviser: Massoud Pedram.
500 $a Source: Dissertation Abstracts International, Volume: 63-12, Section: B, page: 6004.
502 $a Thesis (Ph.D.)--University of Southern California, 2002.
520 $a The new methods and formulations presented in this thesis represent efficient and accurate techniques for the noise analysis and optimization in the mixed-signal VLSI circuits.
520 $a The research presented in this dissertation focuses on noise analysis and optimization in high-frequency mixed-signal VLSI circuits.
520 $a Rapid advances in VLSI technology have enabled us to reduce the minimum feature sizes of transistors to sub-quarter microns and the switching times of MOS transistors to tens of picoseconds or even less. Unfortunately, this comes at a cost. Digital circuits have become subject to the same type of problem that analog integrated circuits have been affected by since their inception. That problem is <italic>noise</italic>. Although device noise sources (i.e., shot noise, flicker noise, thermal noise) are still not an issue in the digital circuits performance, external noise sources (i.e., crosstalk, power/ground (P/G) bounce) significantly degrade the performance and the reliability of digital integrated circuits.
520 $a As a first step toward understanding the noise effects, we explore circuit properties that help us derive closed-form expressions for the capacitive crosstalk noise of RC interconnects as well as the power/ground noise due to the switchings of off-chip drivers.
520 $a We study the effect of the (P/G) noise on the timing jitter of the phase-locked loop (PLL) clock generators. Stochastic models of the P/G noise in VLSI circuits for different values of on-chip decoupling capacitances are presented. The PLL timing jitter is predicted in terms of the statistical properties of the P/G noise.
520 $a Finally, in order to capture all the effects of on-chip interconnect, we provide model-order reduction techniques that use the balanced truncation method and extend this technique to a new spectrally-weighted balanced truncation that reshapes the frequency spectrum and accounts for process variations in order to obtain a new variational spectrally-weighted balanced truncation method.
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