東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Optimization techniques for the next...

Huang, Yu.

FindBook

Google Book

Amazon

博客來

Optimization techniques for the next generation of VLSI test.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Optimization techniques for the next generation of VLSI test./
作者:	Huang, Yu.
面頁冊數:	192 p.
附註:	Source: Dissertation Abstracts International, Volume: 63-04, Section: B, page: 1984.
Contained By:	Dissertation Abstracts International63-04B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3050813
ISBN:	0493654070

Optimization techniques for the next generation of VLSI test.
Huang, Yu.

Optimization techniques for the next generation of VLSI test. - 192 p.

Source: Dissertation Abstracts International, Volume: 63-04, Section: B, page: 1984.

Thesis (Ph.D.)--The University of Iowa, 2002.

In this thesis, several new optimization methodologies are presented for application to the next generation of VLSI test strategies. At-speed test, RTL DFT and core-based SOC test are three research directions studied. The proposed techniques introduced in this thesis can be applied at gate-level, RT-Level and system level, respectively to optimize VLSI test.

ISBN: 0493654070Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Optimization techniques for the next generation of VLSI test.
LDR:03092nam 2200301 a 45 001 936134
005 20110510
008 110510s2002 eng d
020 $a 0493654070
035 $a (UnM)AAI3050813
035 $a AAI3050813
040 $a UnM $c UnM
100 1 $a Huang, Yu. $3 1253425
245 1 0 $a Optimization techniques for the next generation of VLSI test.
300 $a 192 p.
500 $a Source: Dissertation Abstracts International, Volume: 63-04, Section: B, page: 1984.
500 $a Supervisor: Sudhakar M. Reddy.
502 $a Thesis (Ph.D.)--The University of Iowa, 2002.
520 $a In this thesis, several new optimization methodologies are presented for application to the next generation of VLSI test strategies. At-speed test, RTL DFT and core-based SOC test are three research directions studied. The proposed techniques introduced in this thesis can be applied at gate-level, RT-Level and system level, respectively to optimize VLSI test.
520 $a First, a method to select the lengths of functional sequences in a scan-based-BIST scheme is proposed. A functional sequence is a sequence of primary input vectors applied at-speed when the circuit operates as a sequential circuit. The objectives are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The proposed method achieves the above objectives.
520 $a The second methodology presented in this thesis is for inserting scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. RTL code style checking is also considered.
520 $a Finally, several methods are presented to optimize System-on-a-Chip (SOC) testing. A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based SOC designs is presented. The primary objective for concurrent SOC test is to reduce test application time under the constraints of SOC pins and peak power consumption. For a given SOC with various constraints, the objectives being optimized include test resource allocation, test scheduling, wrapper width selection etc. The techniques proposed in this thesis attempt to co-optimize these objectives simultaneously. A set of optimization techniques is introduced to handle different situations to determine an optimal test plan.
590 $a School code: 0096.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a The University of Iowa. $3 1017439
773 0 $t Dissertation Abstracts International $g 63-04B.
790 $a 0096
790 1 0 $a Reddy, Sudhakar M., $e advisor
791 $a Ph.D.
792 $a 2002
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3050813