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A computational framework for IP sel...

Liu, Jian.

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A computational framework for IP selection in SOC designs.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	A computational framework for IP selection in SOC designs./
作者:	Liu, Jian.
面頁冊數:	102 p.
附註:	Adviser: Eugene Shragowitz.
Contained By:	Dissertation Abstracts International63-12B.
標題:	Computer Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3076324
ISBN:	0493967001

A computational framework for IP selection in SOC designs.
Liu, Jian.

A computational framework for IP selection in SOC designs. - 102 p.

Adviser: Eugene Shragowitz.

Thesis (Ph.D.)--University of Minnesota, 2003.

Our work has it as a goal to substantially increase the level of automation in the process of selection of IPs for reuse. This goal is carried out by an Internet based framework called Software Agents for IP selection (SAFIPS).

ISBN: 0493967001Subjects--Topical Terms:

626642
Computer Science.

A computational framework for IP selection in SOC designs.
LDR:02882nam 2200313 a 45 001 933015
005 20110505
008 110505s2003 eng d
020 $a 0493967001
035 $a (UnM)AAI3076324
035 $a AAI3076324
040 $a UnM $c UnM
100 1 $a Liu, Jian. $3 1256755
245 1 0 $a A computational framework for IP selection in SOC designs.
300 $a 102 p.
500 $a Adviser: Eugene Shragowitz.
500 $a Source: Dissertation Abstracts International, Volume: 63-12, Section: B, page: 5936.
502 $a Thesis (Ph.D.)--University of Minnesota, 2003.
520 $a Our work has it as a goal to substantially increase the level of automation in the process of selection of IPs for reuse. This goal is carried out by an Internet based framework called Software Agents for IP selection (SAFIPS).
520 $a The experiments illustrate that the methodology proposed in this work can effectively ease the IP selection process and consequently reduce the SoC design cycle.
520 $a Reuse of IPs (Intellectual Property) becomes an inseparable part of the contemporary design process for System on Chip (SoC). Selection of IPs with the support of existing methods and tools requires a large investment of time on the designers' part. Too many tasks in the process of design reuse are not automated yet.
520 $a In this framework, designers have the flexibility to provide their preferences and constraints during the entire process of IP core selections. This framework can be split into two main modules: parameter evaluations and equivalence checking of two models.
520 $a In the first module, a preliminary evaluation is conducted for IP core parameters and features. Such a process is based on latest efforts and technologies. An XML based dictionary is used to establish an unambiguous identification of IP features. As the designer's preference about IP could have some extent of uncertainty, the fuzzy logic based inference is adopted to provide a friendly and nature way for a designer to express his/her preferences. The second module is for model equivalence checking. We identify the fundamental causes why conventional tools are not effective to provide a good solution in the context of IP selections. Then regular expression based technique is proposed to analyze the simulation waveforms at transaction level. By recognizing transactions, it can reduce the discrepancy caused by timing differences of two models, therefore make the designer easier to judge the differences occurred during the simulation. Such a technique can be used to complement today's design tools.
590 $a School code: 0130.
650 4 $a Computer Science. $3 626642
690 $a 0984
710 2 0 $a University of Minnesota. $3 676231
773 0 $t Dissertation Abstracts International $g 63-12B.
790 $a 0130
790 1 0 $a Shragowitz, Eugene, $e advisor
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3076324