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High-performance techniques for digi...

Kim, Sungwook.

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High-performance techniques for digit-serial applications and LDPC codes.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	High-performance techniques for digit-serial applications and LDPC codes./
作者:	Kim, Sungwook.
面頁冊數:	105 p.
附註:	Adviser: Gerald Edward Sobelman.
Contained By:	Dissertation Abstracts International63-10B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3066378
ISBN:	0493859632

High-performance techniques for digit-serial applications and LDPC codes.
Kim, Sungwook.

High-performance techniques for digit-serial applications and LDPC codes. - 105 p.

Adviser: Gerald Edward Sobelman.

Thesis (Ph.D.)--University of Minnesota, 2002.

Design techniques can be used to increase the performance of digital systems. This thesis introduces several design innovations that load to better performance than previous approaches.

ISBN: 0493859632Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

High-performance techniques for digit-serial applications and LDPC codes.
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100 1 $a Kim, Sungwook. $3 1256089
245 1 0 $a High-performance techniques for digit-serial applications and LDPC codes.
300 $a 105 p.
500 $a Adviser: Gerald Edward Sobelman.
500 $a Source: Dissertation Abstracts International, Volume: 63-10, Section: B, page: 4820.
502 $a Thesis (Ph.D.)--University of Minnesota, 2002.
520 $a Design techniques can be used to increase the performance of digital systems. This thesis introduces several design innovations that load to better performance than previous approaches.
520 $a In the second innovation, an efficient simulation methodology is presented for modeling the time borrowing behavior of skew-tolerant domino circuits.
520 $a In the first technique, digit-serial design is mapped onto skew-tolerant domino circuits. In this design methodology, a digit size of <italic>N</italic> bits is efficiently mapped onto an <italic>N</italic>-phase overlapping clocking scheme, so that <italic>N</italic> bits are processed during each full clock cycle.
520 $a The above design methodologies are evaluated in several important applications. Specifically, a 512-bit modular multiplier, a 16-bit unsigned multiplier, a 16-bit signed multiplier, and an 8-tap FIR filler have been designed and simulated. Comparative results show the effectiveness of the proposed design methodologies.
520 $a Finally, various styles of implementation for Low Density Parity Check (LDPC) codes are developed. We describe a rapid design methodology which automatically generates structural VHDL code for Field Programmable Gate Arrays (FPGAs) using MATLAB. To demonstrate this design methodology, an LDPC encoder and decoder are constructed on a Xilinx Virtex-II device with various block sizes and a code rate of 1/2. An evaluation of the hardware cost and data throughput is given and simulations results for the bit error rate (BER) are obtained as a function of block size.
590 $a School code: 0130.
650 4 $a Engineering, Electronics and Electrical. $3 626636
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710 2 0 $a University of Minnesota. $3 676231
773 0 $t Dissertation Abstracts International $g 63-10B.
790 $a 0130
790 1 0 $a Sobelman, Gerald Edward, $e advisor
791 $a Ph.D.
792 $a 2002
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