語系:
繁體中文
English
說明(常見問題)
回圖書館首頁
手機版館藏查詢
登入
回首頁
切換:
標籤
|
MARC模式
|
ISBD
Deadlock recovery-based router archi...
~
Choi, Yungho.
FindBook
Google Book
Amazon
博客來
Deadlock recovery-based router architectures for high performance networks.
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Deadlock recovery-based router architectures for high performance networks./
作者:
Choi, Yungho.
面頁冊數:
188 p.
附註:
Adviser: Timothy M. Pinkston.
Contained By:
Dissertation Abstracts International63-05B.
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3054723
ISBN:
0493699384
Deadlock recovery-based router architectures for high performance networks.
Choi, Yungho.
Deadlock recovery-based router architectures for high performance networks.
- 188 p.
Adviser: Timothy M. Pinkston.
Thesis (Ph.D.)--University of Southern California, 2001.
Multiprocessor systems have been developed to efficiently solve complex and large scientific problems. Generally, these systems have a critical component, i.e., interconnection network, which significantly affects system performance by determining the communication capability of multiprocessor systems. In recent years, with the emergence of bandwidth-hungry applications and multi-GHz processors, the demand on high performance interconnection networks has been increased to meet rapidly growing communication needs of multiprocessor systems.
ISBN: 0493699384Subjects--Topical Terms:
626636
Engineering, Electronics and Electrical.
Deadlock recovery-based router architectures for high performance networks.
LDR
:03250nam 2200301 a 45
001
932321
005
20110505
008
110505s2001 eng d
020
$a
0493699384
035
$a
(UnM)AAI3054723
035
$a
AAI3054723
040
$a
UnM
$c
UnM
100
1
$a
Choi, Yungho.
$3
1256067
245
1 0
$a
Deadlock recovery-based router architectures for high performance networks.
300
$a
188 p.
500
$a
Adviser: Timothy M. Pinkston.
500
$a
Source: Dissertation Abstracts International, Volume: 63-05, Section: B, page: 2502.
502
$a
Thesis (Ph.D.)--University of Southern California, 2001.
520
$a
Multiprocessor systems have been developed to efficiently solve complex and large scientific problems. Generally, these systems have a critical component, i.e., interconnection network, which significantly affects system performance by determining the communication capability of multiprocessor systems. In recent years, with the emergence of bandwidth-hungry applications and multi-GHz processors, the demand on high performance interconnection networks has been increased to meet rapidly growing communication needs of multiprocessor systems.
520
$a
To satisfy this demand, routing algorithms must fully utilize network resources while efficiently handling message deadlock which leads to the halting of an entire system. There are largely two classes of routing algorithms according to the way deadlocks can be dealt: deadlock avoidance-based and deadlock recovery-based routing algorithms. Deadlock avoidance-based networks prevent deadlocks by enforcing routing restrictions, which hampers routing adaptivity and, therefore, limits network performance. To overcome this problem, recently a number of deadlock recovery-based networks have been proposed, which maximize routing adaptivity and, thus, significantly increase network performance. But, the increased routing adaptivity could lead to slower and more complicated router architectures, degrading overall network performance.
520
$a
In order to minimize the architecture complexity of deadlock recovery-based routers and to maximize network performance, this dissertation optimizes deadlock recovery-based router architectures by proposing two router component design solutions, i.e., partitioned crossbar designs and enhanced dynamically allocated multi-queue designs. These solutions significantly reduce the architecture complexity of deadlock recovery-based routers while fully benefiting from their capability, leading to optimal deadlock recovery-based router architectures.
520
$a
Through extensive evaluations of various router architectures, this dissertation verifies that the true fully adaptive routing capability of deadlock recovery schemes can be efficiently implemented in routers and, hence, their superior network performance can be realized. Finally, this work demonstrates the feasibility of some of the proposed router architectures by implementing the WARRP router.
590
$a
School code: 0208.
650
4
$a
Engineering, Electronics and Electrical.
$3
626636
690
$a
0544
710
2 0
$a
University of Southern California.
$3
700129
773
0
$t
Dissertation Abstracts International
$g
63-05B.
790
$a
0208
790
1 0
$a
Pinkston, Timothy M.,
$e
advisor
791
$a
Ph.D.
792
$a
2001
856
4 0
$u
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3054723
筆 0 讀者評論
館藏地:
全部
電子資源
出版年:
卷號:
館藏
1 筆 • 頁數 1 •
1
條碼號
典藏地名稱
館藏流通類別
資料類型
索書號
使用類型
借閱狀態
預約狀態
備註欄
附件
W9103009
電子資源
11.線上閱覽_V
電子書
EB W9103009
一般使用(Normal)
在架
0
1 筆 • 頁數 1 •
1
多媒體
評論
新增評論
分享你的心得
Export
取書館
處理中
...
變更密碼
登入