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PITIA: An FPGA for throughput-inten...

Singh, Amit.

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PITIA: An FPGA for throughput-intensive applications.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	PITIA: An FPGA for throughput-intensive applications./
Author:	Singh, Amit.
Description:	145 p.
Notes:	Chairperson: Malgorzata Marek-Sadowska.
Contained By:	Dissertation Abstracts International63-02B.
Subject:	Computer Science. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3041249
ISBN:	0493545972

PITIA: An FPGA for throughput-intensive applications.
Singh, Amit.

PITIA: An FPGA for throughput-intensive applications. - 145 p.

Chairperson: Malgorzata Marek-Sadowska.

Thesis (Ph.D.)--University of California, Santa Barbara, 2002.

In the past decade, Field Programmable Gate Arrays (FPGAs) have become increasingly popular for their ability to provide low cost solutions in a variety of design applications. FPGAs have low design costs and a short time-to-market which makes them an attractive alternative to custom logic. The advent of Deep Sub-Micron (DSM) technologies has increased this attraction and has given rise to million-gate FPGAs. However, most commercial FPGAs cannot handle applications that require very high throughput. These throughput-intensive applications mostly occur in the real-time Digital Signal Processing (DSP) and datapath domains. FPGAs cannot handle such applications because they have a general-purpose architectural nature which forces them to be much slower (often as much as ten times) than custom logic. In addition, modern commercial FPGAs are encountering the same physical design issues that have faced their ASIC counterparts for over a decade. Timing (throughput), area and power dissipation remain the three most important factors that prevent the mass acceptance of FPGAs.

ISBN: 0493545972Subjects--Topical Terms:

626642
Computer Science.

PITIA: An FPGA for throughput-intensive applications.
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020 $a 0493545972
035 $a (UnM)AAI3041249
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040 $a UnM $c UnM
100 1 $a Singh, Amit. $3 1254529
245 1 0 $a PITIA: An FPGA for throughput-intensive applications.
300 $a 145 p.
500 $a Chairperson: Malgorzata Marek-Sadowska.
500 $a Source: Dissertation Abstracts International, Volume: 63-02, Section: B, page: 0951.
502 $a Thesis (Ph.D.)--University of California, Santa Barbara, 2002.
520 $a In the past decade, Field Programmable Gate Arrays (FPGAs) have become increasingly popular for their ability to provide low cost solutions in a variety of design applications. FPGAs have low design costs and a short time-to-market which makes them an attractive alternative to custom logic. The advent of Deep Sub-Micron (DSM) technologies has increased this attraction and has given rise to million-gate FPGAs. However, most commercial FPGAs cannot handle applications that require very high throughput. These throughput-intensive applications mostly occur in the real-time Digital Signal Processing (DSP) and datapath domains. FPGAs cannot handle such applications because they have a general-purpose architectural nature which forces them to be much slower (often as much as ten times) than custom logic. In addition, modern commercial FPGAs are encountering the same physical design issues that have faced their ASIC counterparts for over a decade. Timing (throughput), area and power dissipation remain the three most important factors that prevent the mass acceptance of FPGAs.
520 $a In this dissertation, we address the issues outlined above. Specifically, we propose a novel high throughput FPGA architecture, <italic>PITIA</italic>, which uses the concept of Wave Steering to achieve throughputs in excess of 500 MHz in 0.25μm CMOS technology for a range of regular DSP designs. We present a novel method of circuit signal reordering for area and power reduction in PITIA. We show that efficient circuit clustering can positively impact area, power, and timing in PITIA as well as other clustered FPGAs. By characterizing both the design and architecture complexity and incorporating it into placement tools, we can further reduce area utilization, and power consumption. Finally, based on the fanout distribution of circuits, we propose a novel way of designing the programmable interconnect schemes to achieve both area reduction and timing closure in clustered FPGAs.
590 $a School code: 0035.
650 4 $a Computer Science. $3 626642
650 4 $a Engineering, Electronics and Electrical. $3 626636
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710 2 0 $a University of California, Santa Barbara. $3 1017586
773 0 $t Dissertation Abstracts International $g 63-02B.
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790 1 0 $a Marek-Sadowska, Malgorzata, $e advisor
791 $a Ph.D.
792 $a 2002
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3041249