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The gm/ID Methodology, a sizing tool...

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The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuits = the semi-empirical and compact model approaches /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuits/ by Paul Jespers.
其他題名:	the semi-empirical and compact model approaches /
作者:	Jespers, Paul.
出版者:	Boston, MA :Springer Science+Business Media, LLC, : 2010.,
面頁冊數:	xvi, 171 p. :ill., digital ;24 cm.
叢書名:	Analog circuits and signal processing
Contained By:	Springer eBooks
標題:	Linear integrated circuits - Design and construction. -
電子資源:	http://dx.doi.org/10.1007/978-0-387-47101-3
ISBN:	9780387471006 (paper)

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuits = the semi-empirical and compact model approaches /
Jespers, Paul.

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuitsthe semi-empirical and compact model approaches /[electronic resource] :by Paul Jespers. - Boston, MA :Springer Science+Business Media, LLC,2010. - xvi, 171 p. :ill., digital ;24 cm. - Analog circuits and signal processing.

ISBN: 9780387471006 (paper)Subjects--Topical Terms:

655292
Linear integrated circuits
--Design and construction.

LC Class. No.: TK7871.99.M44 / J47 2010

Dewey Class. No.: 621.3815

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuits = the semi-empirical and compact model approaches /
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