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Reducing main memory access latency ...

Michigan Technological University.

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Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms./
作者:	Shao, Jun.
面頁冊數:	174 p.
附註:	Adviser: Brian T. Davis.
Contained By:	Dissertation Abstracts International67-12B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3245355

Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms.
Shao, Jun.

Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms. - 174 p.

Adviser: Brian T. Davis.

Thesis (Ph.D.)--Michigan Technological University, 2006.

As the performance gap between microprocessors and memory continues to increase, main memory accesses result in long latencies which become a factor limiting system performance. Previous studies show that main memory access streams contain significant localities and SDRAM devices provide parallelism through multiple banks and channels. These locality and parallelism have not been exploited thoroughly by conventional memory controllers. In this thesis, SDRAM address mapping techniques and memory access reordering mechanisms are studied and applied to memory controller design with the goal of reducing observed main memory access latency.Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms.
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245 1 0 $a Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms.
300 $a 174 p.
500 $a Adviser: Brian T. Davis.
500 $a Source: Dissertation Abstracts International, Volume: 67-12, Section: B, page: 7281.
502 $a Thesis (Ph.D.)--Michigan Technological University, 2006.
520 $a As the performance gap between microprocessors and memory continues to increase, main memory accesses result in long latencies which become a factor limiting system performance. Previous studies show that main memory access streams contain significant localities and SDRAM devices provide parallelism through multiple banks and channels. These locality and parallelism have not been exploited thoroughly by conventional memory controllers. In this thesis, SDRAM address mapping techniques and memory access reordering mechanisms are studied and applied to memory controller design with the goal of reducing observed main memory access latency.
520 $a The proposed bit-reversal address mapping attempts to distribute main memory accesses evenly in the SDRAM address space to enable bank parallelism. As memory accesses to unique banks are interleaved, the access latencies are partially hidden and therefore reduced. With the consideration of cache conflict misses, bit-reversal address mapping is able to direct potential row conflicts to different banks, further improving the performance.
520 $a The proposed burst scheduling is a novel access reordering mechanism, which creates bursts by clustering accesses directed to the same rows of the same banks. Subjected to a threshold, reads are allowed to preempt writes and qualified writes are piggybacked at the end of the bursts. A sophisticated access scheduler selects accesses based on priorities and interleaves accesses to maximize the SDRAM data bus utilization. Consequentially burst scheduling reduces row conflict rate, increasing and exploiting the available row locality.
520 $a Using a revised SimpleScalar and M5 simulator, both techniques are evaluated and compared with existing academic and industrial solutions. With SPEC CPU2000 benchmarks, bit-reversal reduces the execution time by 14% on average over traditional page interleaving address mapping. Burst scheduling also achieves a 15% reduction in execution time over conventional bank in order scheduling. Working constructively together, bit-reversal and burst scheduling successfully achieve a 19% speedup across simulated benchmarks.
590 $a School code: 0129.
650 4 $a Engineering, Electronics and Electrical. $3 626636
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710 2 $a Michigan Technological University. $3 1032921
773 0 $t Dissertation Abstracts International $g 67-12B.
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791 $a Ph.D.
792 $a 2006
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