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IC design for reliability.

The University of Texas at Austin., Electrical Engineering.

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IC design for reliability.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	IC design for reliability./
作者:	Zhang, Bin.
面頁冊數:	104 p.
附註:	Adviser: Michael Orshansky.
Contained By:	Dissertation Abstracts International70-08B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3371774
ISBN:	9781109333947

IC design for reliability.
Zhang, Bin.

IC design for reliability. - 104 p.

Adviser: Michael Orshansky.

Thesis (Ph.D.)--The University of Texas at Austin, 2009.

As the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severity of reliability challenges and higher error rates due to transient upsets favor higher-level design for reliability (DFR). In this work, we develop several methods for DFR at the circuit level.

ISBN: 9781109333947Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

IC design for reliability.
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100 1 $a Zhang, Bin. $3 1026825
245 1 0 $a IC design for reliability.
300 $a 104 p.
500 $a Adviser: Michael Orshansky.
500 $a Source: Dissertation Abstracts International, Volume: 70-08, Section: B, page: .
502 $a Thesis (Ph.D.)--The University of Texas at Austin, 2009.
520 $a As the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severity of reliability challenges and higher error rates due to transient upsets favor higher-level design for reliability (DFR). In this work, we develop several methods for DFR at the circuit level.
520 $a A major source of transient errors is the single event upset (SEU). SEUs are caused by high-energy particles present in the cosmic rays or emitted by radioactive contaminants in the chip packaging materials. When these particles hit a N+/P+ depletion region of an MOS transistor, they may generate a temporary logic fault. Depending on where the MOS transistor is located and what state the circuit is at, an SEU may result in a circuit-level error. We analyze SEUs both in combinational logic and memories (SRAM). For combinational logic circuit, we propose FASER, a Fast Analysis tool of Soft ERror susceptibility for cell-based designs. The efficiency of FASER is achieved through its static and vector-less nature. In order to evaluate the impact of SEU on SRAM, a theory for estimating dynamic noise margins is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closed-form expression.
520 $a Among the many permanent failure mechanisms that include time-dependent oxide breakdown (TDDB), electro-migration (EM), hot carrier effect (HCE), and negative bias temperature instability (NBTI), NBTI has recently become important. Therefore, the main focus of our work is NBTI. NBTI occurs when the gate of PMOS is negatively biased. The voltage stress across the gate generates interface traps, which degrade the threshold voltage of PMOS. The degraded PMOS may eventually fail to meet timing requirement and cause functional errors. NBTI becomes severe at elevated temperatures. In this dissertation, we propose a NBTI degradation model that takes into account the temperature variation on the chip and gives the accurate estimation of the degraded threshold voltage.
520 $a In order to account for the degradation of devices, traditional design methods add guard-bands to ensure that the circuit will function properly during its lifetime. However, the worst-case based guard-bands lead to significant penalty in performance. In this dissertation, we propose an effective macromodel-based reliability tracking and management framework, based on a hybrid network of on-chip sensors, consisting of temperature sensors and ring oscillators. The model is concerned specifically with NBTI-induced transistor aging. The key feature of our work, in contrast to the traditional tracking techniques that rely solely on direct measurement of the increase of threshold voltage or circuit delay, is an explicit macromodel which maps operating temperature to circuit degradation (the increase of circuit delay). The macromodel allows for cost-effective tracking of reliability using temperature sensors and is also essential for enabling the control loop of the reliability management system.
520 $a The developed methods improve the over-conservatism of the device-level, worst-case reliability estimation techniques. As the severity of reliability challenges continue to grow with technology scaling, it will become more important for circuit designers/CAD tools to be equipped with the developed methods.
590 $a School code: 0227.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a The University of Texas at Austin. $b Electrical Engineering. $3 1026824
773 0 $t Dissertation Abstracts International $g 70-08B.
790 $a 0227
790 1 0 $a Arapostathis, Ari $e committee member
790 1 0 $a Arbogast, Todd $e committee member
790 1 0 $a Lee, Jack $e committee member
790 1 0 $a Orshansky, Michael $e committee member
790 1 0 $a Orshansky, Michael, $e advisor
790 1 0 $a Pan, David $e committee member
790 1 0 $a Touba, Nur $e committee member
791 $a Ph.D.
792 $a 2009
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3371774