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Systemverilog for verification = a guide to learning the testbench language features /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Systemverilog for verification/ by Chris Spear.
其他題名:	a guide to learning the testbench language features /
作者:	Spear, Chris.
出版者:	Boston, MA :Springer Science+Business Media, LLC, : 2008.,
面頁冊數:	436 p. :ill., digital ;25 cm.
Contained By:	Springer eBooks
標題:	Integrated circuits - Verification. -
電子資源:	http://dx.doi.org/10.1007/978-0-387-76530-3http://dx.doi.org/10.1007/978-0-387-76530-3
ISBN:	9780387765297 (paper)

Systemverilog for verification = a guide to learning the testbench language features /
Spear, Chris.

Systemverilog for verificationa guide to learning the testbench language features /[electronic resource] :by Chris Spear. - 2nd ed. - Boston, MA :Springer Science+Business Media, LLC,2008. - 436 p. :ill., digital ;25 cm.

ISBN: 9780387765297 (paper)Subjects--Topical Terms:

827163
Integrated circuits
--Verification.

Dewey Class. No.: 621.392

Systemverilog for verification = a guide to learning the testbench language features /
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