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Integrated circuit design = tape-out...

Ortega Cisneros, Susana.

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Integrated circuit design = tape-out process with open-source tools /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Integrated circuit design/ by Susana Ortega Cisneros, Emilio Isaac Baungarten Leon, Pedro Mejia Alvarez.
其他題名:	tape-out process with open-source tools /
作者:	Ortega Cisneros, Susana.
其他作者:	Baungarten Leon, Emilio Isaac.
出版者:	Cham :Springer Nature Switzerland : : 2025.,
面頁冊數:	xi, 111 p. :ill., digital ;24 cm.
內容註:	1: Introduction -- 2: Physical Design Flow -- 3: Process Design Kit -- 4: Introduction to OpenLane -- 5: Macro-Cells and RAM-Cells with OpenLane -- 6: Exploring OpenLane through Case Studies and Exercises -- 7: Caravel.
Contained By:	Springer Nature eBook
標題:	Integrated circuits - Design and construction. -
電子資源:	https://doi.org/10.1007/978-3-031-92108-7
ISBN:	9783031921087

Integrated circuit design = tape-out process with open-source tools /
Ortega Cisneros, Susana.

Integrated circuit designtape-out process with open-source tools /[electronic resource] :by Susana Ortega Cisneros, Emilio Isaac Baungarten Leon, Pedro Mejia Alvarez. - Cham :Springer Nature Switzerland :2025. - xi, 111 p. :ill., digital ;24 cm. - SpringerBriefs in computer science,2191-5776. - SpringerBriefs in computer science..

1: Introduction -- 2: Physical Design Flow -- 3: Process Design Kit -- 4: Introduction to OpenLane -- 5: Macro-Cells and RAM-Cells with OpenLane -- 6: Exploring OpenLane through Case Studies and Exercises -- 7: Caravel.

This book provides a structured and comprehensive pathway through the complexities of Electronic Design Automation (EDA) tools and processes. It focuses on OpenLane and Caravel EDA tools, due to their current major role in the open-source IC design ecosystem. OpenLane provides a robust and flexible platform that automates the entire digital design flow from Register Transfer Level (RTL) to Graphic Data System II (GDSII), making it an ideal tool for teaching and learning the physical design process. Caravel, on the other hand, serves as an open-source System on a Chip (SoC) platform, allowing designers to integrate and test their designs in a versatile, real-world environment. It complements OpenLane by enabling users to package and validate their designs, bridging the gap between theoretical knowledge and practical implementation. Together, these tools provide a way to understand the full tape-out process in a way that is accessible to students, researchers, and professionals alike.

ISBN: 9783031921087

Standard No.: 10.1007/978-3-031-92108-7doiSubjects--Topical Terms:

658490
Integrated circuits
--Design and construction.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

Integrated circuit design = tape-out process with open-source tools /
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