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Hardware security = a look into the future /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Hardware security/ by Mark Tehranipoor ... [et al.].
其他題名:	a look into the future /
其他作者:	Tehranipoor, Mohammad H.
出版者:	Cham :Springer Nature Switzerland : : 2024.,
面頁冊數:	xxi, 525 p. :ill. (some col.), digital ;24 cm.
內容註:	Chapter 1 Quantifiable Assurance in Hardware -- Chapter 2 Advances in Logic Locking -- Chapter 3 Rethinking Hardware Watermark -- Chapter 4 SoC Security Verification using Fuzz, Penetration, and AI Testing -- Chapter 5 Runtime SoC Security Validation -- Chapter 6 Large Language Models for SoC Security -- Chapter 7 Power Side-channel Evaluation in Post-Quantum Cryptography -- Chapter 8 Digital Twin for Secure Semiconductor Lifecycle Management -- Chapter 9 Secure Physical Design -- Chapter 10 Secure Heterogeneous Integration -- Chapter 11 Materials for Hardware Security.
Contained By:	Springer Nature eBook
標題:	Computer security. -
電子資源:	https://doi.org/10.1007/978-3-031-58687-3
ISBN:	9783031586873

Hardware security = a look into the future /
Hardware securitya look into the future /[electronic resource] :by Mark Tehranipoor ... [et al.]. - Cham :Springer Nature Switzerland :2024. - xxi, 525 p. :ill. (some col.), digital ;24 cm.

Chapter 1 Quantifiable Assurance in Hardware -- Chapter 2 Advances in Logic Locking -- Chapter 3 Rethinking Hardware Watermark -- Chapter 4 SoC Security Verification using Fuzz, Penetration, and AI Testing -- Chapter 5 Runtime SoC Security Validation -- Chapter 6 Large Language Models for SoC Security -- Chapter 7 Power Side-channel Evaluation in Post-Quantum Cryptography -- Chapter 8 Digital Twin for Secure Semiconductor Lifecycle Management -- Chapter 9 Secure Physical Design -- Chapter 10 Secure Heterogeneous Integration -- Chapter 11 Materials for Hardware Security.

This book provides a look into the future of hardware and microelectronics security, with an emphasis on potential directions in security-aware design, security verification and validation, building trusted execution environments, and physical assurance. The book emphasizes some critical questions that must be answered in the domain of hardware and microelectronics security in the next 5-10 years: (i) The notion of security must be migrated from IP-level to system-level; (ii) What would be the future of IP and IC protection against emerging threats; (iii) How security solutions could be migrated/expanded from SoC-level to SiP-level; (iv) the advances in power side-channel analysis with emphasis on post-quantum cryptography algorithms; (v) how to enable digital twin for secure semiconductor lifecycle management; and (vi) how physical assurance will look like with considerations of emerging technologies. The main aim of this book is to serve as a comprehensive and concise roadmap for new learners and educators navigating the evolving research directions in the domain of hardware and microelectronic securities. Overall, throughout 11 chapters, the book provides numerous frameworks, countermeasures, security evaluations, and roadmaps for the future of hardware security. Discusses the future of hardware and microelectronics security, the risks, challenges and potential countermeasures; Describes a physical design roadmap, incorporating emerging technologies into security solutions; Uses security-related metrics to explain how assurance can be quantified, from IP to security levels.

ISBN: 9783031586873

Standard No.: 10.1007/978-3-031-58687-3doiSubjects--Topical Terms:

540555
Computer security.

LC Class. No.: QA76.9.A25

Dewey Class. No.: 005.8

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505 0 $a Chapter 1 Quantifiable Assurance in Hardware -- Chapter 2 Advances in Logic Locking -- Chapter 3 Rethinking Hardware Watermark -- Chapter 4 SoC Security Verification using Fuzz, Penetration, and AI Testing -- Chapter 5 Runtime SoC Security Validation -- Chapter 6 Large Language Models for SoC Security -- Chapter 7 Power Side-channel Evaluation in Post-Quantum Cryptography -- Chapter 8 Digital Twin for Secure Semiconductor Lifecycle Management -- Chapter 9 Secure Physical Design -- Chapter 10 Secure Heterogeneous Integration -- Chapter 11 Materials for Hardware Security.
520 $a This book provides a look into the future of hardware and microelectronics security, with an emphasis on potential directions in security-aware design, security verification and validation, building trusted execution environments, and physical assurance. The book emphasizes some critical questions that must be answered in the domain of hardware and microelectronics security in the next 5-10 years: (i) The notion of security must be migrated from IP-level to system-level; (ii) What would be the future of IP and IC protection against emerging threats; (iii) How security solutions could be migrated/expanded from SoC-level to SiP-level; (iv) the advances in power side-channel analysis with emphasis on post-quantum cryptography algorithms; (v) how to enable digital twin for secure semiconductor lifecycle management; and (vi) how physical assurance will look like with considerations of emerging technologies. The main aim of this book is to serve as a comprehensive and concise roadmap for new learners and educators navigating the evolving research directions in the domain of hardware and microelectronic securities. Overall, throughout 11 chapters, the book provides numerous frameworks, countermeasures, security evaluations, and roadmaps for the future of hardware security. Discusses the future of hardware and microelectronics security, the risks, challenges and potential countermeasures; Describes a physical design roadmap, incorporating emerging technologies into security solutions; Uses security-related metrics to explain how assurance can be quantified, from IP to security levels.
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