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Investigation of Ultra-Thin Dielectrics on Coupled Capacitive and Inductive Effects in Laterally Conducting Power Device Packaging.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Investigation of Ultra-Thin Dielectrics on Coupled Capacitive and Inductive Effects in Laterally Conducting Power Device Packaging./
作者:	Cheng, Tzu-Hsuan.
面頁冊數:	1 online resource (168 pages)
附註:	Source: Dissertations Abstracts International, Volume: 84-10, Section: B.
Contained By:	Dissertations Abstracts International84-10B.
標題:	Mechanical properties. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=30364019click for full text (PQDT)
ISBN:	9798377687337

Investigation of Ultra-Thin Dielectrics on Coupled Capacitive and Inductive Effects in Laterally Conducting Power Device Packaging.
Cheng, Tzu-Hsuan.

Investigation of Ultra-Thin Dielectrics on Coupled Capacitive and Inductive Effects in Laterally Conducting Power Device Packaging. - 1 online resource (168 pages)

Source: Dissertations Abstracts International, Volume: 84-10, Section: B.

Thesis (M.E.)--North Carolina State University, 2023.

Includes bibliographical references

With the confluence of Wide Bandgap (WBG) power semiconductor devices' superior characteristics, trends of high efficiency, low volume and weight, and cost-effective solution for power electronics systems, the demands for the advanced power packaging are growing rapidly. Laterally conducting Gallium Nitride/Aluminum Gallium Nitride (GaN/AlGaN) heterojunction transistor is one of the WBG power devices and holds fast-switching characteristics enabling high efficiency and small form factor. To not limit the fast-switching advantages, an ultra-low inductance interconnection configuration for a half-bridge power module is proposed. This configuration includes an optimal power device metalized pad layout and a novel power module structure. The superior performance is realized through a power module case study utilizing multipad GaN/AlGaN power devices and an ultra-thin dielectric interposer. Ultra-low inductance is achieved by parallel-plate multi-loop interconnection which facilitates a significant magnetic field cancellation. To achieve higher density and fulfill insulation requirements, a heterogeneously integrated power interposer (HIPI) with ultra-thin dielectric is employed between power devices for attainingminimum insulation and integratingpower switches, gate drivers, and passive devices into a compact power module. HIPI is a metal-clad insulated substrate that manages all the electrical routing and interconnectionPackaging designers usually compare the power loop parasitic inductance and thermal resistance junction-to-case with other designs to showcase their packaging performances are as better than all the others'. Nevertheless, with different semiconductor device technologies (e.g., vertical SiC and lateral GaN), voltage ratings, current ratings, and numbers of power devices per switch makes the comparison meaningless. Therefore, this study establishes novel P and T factors that can fairly compare power loop inductance and thermal resistance respectively by normalizing the differences mentioned above. Moreover, placing power switches close together is a common way to reduce parasitic inductance due to a shorter interconnection distance. However, small space between switches induces strong thermal coupling and limited thermal spreading, leading to poor heat dissipating capability. As a result, a power module figure of merit (PMFOM) is proposed to measure the trade-off and fairly compare the overall electrical and thermal packaging performances by combining P and T factors together. The electrical and thermal performances of the power module case study are compared with other works by utilizing the proposed PMFOM.Ultra-thin dielectrics attract significant attention not only because of achievable smallform factors but also the capabilities to manage electrical and thermal characteristics. However, due to the thin dielectric feature, the parasitic capacitance induced common-mode (CM) current is magnified compared with traditional thick ceramic-plate substrates. This study also integrates an interstitial conductor layer (or shielding layer) into the dielectric layers for CM noise reduction by transferring the capacitive current to power loop decoupling capacitors inside the module rather than flowing to ground. This study conducts comprehensive analyses on defining parasitics and simplifying impedance network of theCM noise model which can be applied to any type of power circuit topologies and power module structures.The analytical models of the ground current and resonant frequency are key factors for the design guidelines of CM noise suppression. In addition to the methodology development, this study also provides the optimization processes on conductor layer pattern designs, dielectric thicknesses, and dielectric material selection for designing ultrathin dielectric substrates.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2023

Mode of access: World Wide Web

ISBN: 9798377687337Subjects--Topical Terms:

3549505
Mechanical properties.
Index Terms--Genre/Form:

542853
Electronic books.

Investigation of Ultra-Thin Dielectrics on Coupled Capacitive and Inductive Effects in Laterally Conducting Power Device Packaging.
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520 $a With the confluence of Wide Bandgap (WBG) power semiconductor devices' superior characteristics, trends of high efficiency, low volume and weight, and cost-effective solution for power electronics systems, the demands for the advanced power packaging are growing rapidly. Laterally conducting Gallium Nitride/Aluminum Gallium Nitride (GaN/AlGaN) heterojunction transistor is one of the WBG power devices and holds fast-switching characteristics enabling high efficiency and small form factor. To not limit the fast-switching advantages, an ultra-low inductance interconnection configuration for a half-bridge power module is proposed. This configuration includes an optimal power device metalized pad layout and a novel power module structure. The superior performance is realized through a power module case study utilizing multipad GaN/AlGaN power devices and an ultra-thin dielectric interposer. Ultra-low inductance is achieved by parallel-plate multi-loop interconnection which facilitates a significant magnetic field cancellation. To achieve higher density and fulfill insulation requirements, a heterogeneously integrated power interposer (HIPI) with ultra-thin dielectric is employed between power devices for attainingminimum insulation and integratingpower switches, gate drivers, and passive devices into a compact power module. HIPI is a metal-clad insulated substrate that manages all the electrical routing and interconnectionPackaging designers usually compare the power loop parasitic inductance and thermal resistance junction-to-case with other designs to showcase their packaging performances are as better than all the others'. Nevertheless, with different semiconductor device technologies (e.g., vertical SiC and lateral GaN), voltage ratings, current ratings, and numbers of power devices per switch makes the comparison meaningless. Therefore, this study establishes novel P and T factors that can fairly compare power loop inductance and thermal resistance respectively by normalizing the differences mentioned above. Moreover, placing power switches close together is a common way to reduce parasitic inductance due to a shorter interconnection distance. However, small space between switches induces strong thermal coupling and limited thermal spreading, leading to poor heat dissipating capability. As a result, a power module figure of merit (PMFOM) is proposed to measure the trade-off and fairly compare the overall electrical and thermal packaging performances by combining P and T factors together. The electrical and thermal performances of the power module case study are compared with other works by utilizing the proposed PMFOM.Ultra-thin dielectrics attract significant attention not only because of achievable smallform factors but also the capabilities to manage electrical and thermal characteristics. However, due to the thin dielectric feature, the parasitic capacitance induced common-mode (CM) current is magnified compared with traditional thick ceramic-plate substrates. This study also integrates an interstitial conductor layer (or shielding layer) into the dielectric layers for CM noise reduction by transferring the capacitive current to power loop decoupling capacitors inside the module rather than flowing to ground. This study conducts comprehensive analyses on defining parasitics and simplifying impedance network of theCM noise model which can be applied to any type of power circuit topologies and power module structures.The analytical models of the ground current and resonant frequency are key factors for the design guidelines of CM noise suppression. In addition to the methodology development, this study also provides the optimization processes on conductor layer pattern designs, dielectric thicknesses, and dielectric material selection for designing ultrathin dielectric substrates.
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