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Elastic Processing and Hardware Architectures for Machine Learning.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Elastic Processing and Hardware Architectures for Machine Learning./
Author:	Liu, Liu.
Description:	1 online resource (209 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 84-02, Section: B.
Contained By:	Dissertations Abstracts International84-02B.
Subject:	Computer science. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=29067714click for full text (PQDT)
ISBN:	9798841775751

Elastic Processing and Hardware Architectures for Machine Learning.
Liu, Liu.

Elastic Processing and Hardware Architectures for Machine Learning. - 1 online resource (209 pages)

Source: Dissertations Abstracts International, Volume: 84-02, Section: B.

Thesis (Ph.D.)--University of California, Santa Barbara, 2022.

Includes bibliographical references

Machine Learning (ML) techniques, especially Deep Neural Networks (DNNs), have been driving innovations in many application domains. These breakthroughs are powered by the computational improvements in processor technology driven by Moore's Law. However, the need for computational resources is insatiable when applying ML to large- scale real-world problems. Energy efficiency is another major concern of large-scale ML. The enormous energy consumption of ML models not only increases costs in data-centers and decreases battery life of mobile devices but also has a severe environmental impact. Entering the post-Moore's Law era, how to keep up performance and energy-efficiency with the scaling of ML remains challenging.This dissertation addresses the performance and energy-efficiency challenges of ML. The thesis can be encapsulated in a few questions. Do we need all the computations and data movements involved in conventional ML processing? Does redundancy exist at the hardware level? How can we better approach large-scale ML problems with new computing paradigms? This dissertation presents how to explore the elasticity in ML processing and hardware architectures: from the algorithm perspective, redundancy-aware processing methods are proposed for DNN training and inference, as well as large-scale classification problems and long-range Transformers; from the architecture perspective, balanced, specialized, and flexible designs are presented to improve efficiency.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2023

Mode of access: World Wide Web

ISBN: 9798841775751Subjects--Topical Terms:

523869
Computer science.
Subjects--Index Terms:

Domain-specific architecturesIndex Terms--Genre/Form:

542853
Electronic books.

Elastic Processing and Hardware Architectures for Machine Learning.
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500 $a Advisor: Xie, Yuan; Ding, Yufei.
502 $a Thesis (Ph.D.)--University of California, Santa Barbara, 2022.
504 $a Includes bibliographical references
520 $a Machine Learning (ML) techniques, especially Deep Neural Networks (DNNs), have been driving innovations in many application domains. These breakthroughs are powered by the computational improvements in processor technology driven by Moore's Law. However, the need for computational resources is insatiable when applying ML to large- scale real-world problems. Energy efficiency is another major concern of large-scale ML. The enormous energy consumption of ML models not only increases costs in data-centers and decreases battery life of mobile devices but also has a severe environmental impact. Entering the post-Moore's Law era, how to keep up performance and energy-efficiency with the scaling of ML remains challenging.This dissertation addresses the performance and energy-efficiency challenges of ML. The thesis can be encapsulated in a few questions. Do we need all the computations and data movements involved in conventional ML processing? Does redundancy exist at the hardware level? How can we better approach large-scale ML problems with new computing paradigms? This dissertation presents how to explore the elasticity in ML processing and hardware architectures: from the algorithm perspective, redundancy-aware processing methods are proposed for DNN training and inference, as well as large-scale classification problems and long-range Transformers; from the architecture perspective, balanced, specialized, and flexible designs are presented to improve efficiency.
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