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Integration of a Dynamic Offset Testbench in 0.18UM CMOS to Measure Comparator Offsets.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Integration of a Dynamic Offset Testbench in 0.18UM CMOS to Measure Comparator Offsets./
作者:	Aung, Nan.
面頁冊數:	1 online resource (45 pages)
附註:	Source: Masters Abstracts International, Volume: 83-05.
Contained By:	Masters Abstracts International83-05.
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28492933click for full text (PQDT)
ISBN:	9798480679403

Integration of a Dynamic Offset Testbench in 0.18UM CMOS to Measure Comparator Offsets.
Aung, Nan.

Integration of a Dynamic Offset Testbench in 0.18UM CMOS to Measure Comparator Offsets. - 1 online resource (45 pages)

Source: Masters Abstracts International, Volume: 83-05.

Thesis (M.Sc.)--California State University, Sacramento, 2021.

Includes bibliographical references

The Dynamic Offset Test Bench (DOTB) is a simulation technique that yields values for the input-referred offset voltage of latching comparators including both static and dynamic effects [2]. This project focuses on an implementation of the DOTB in a 0.18um CMOS silicon integrated circuit. This chip will provide a test vehicle to compare the measured performance of multiple comparators to their simulated performance. Such comparisons will help to validate the DOTB simulation technique and will provide insights into the operation of latching comparators.The comparators to be tested comprise an array of 16 comparators incorporating various intentional imperfections. A separate comparator is also included on chip to allow the DC bias voltages inside the comparator to be measured. It should be noted that the comparator and charge pump circuits were previously designed by other graduate students at Sacramento State [6].This work involved the integration of the comparator array and charge pump into a complete integrated circuit test chip, as well as the design of a 4-to-16 digital decoder, the bias circuits required for the comparator, and two 16-to-1 multiplexers. The top-level design had to accommodate the overall functionality of the various test modes required.Schematics were captured using Cadence Virtuoso, and simulations were performed to verify performance across process, supply voltage, and temperature (PVT) variations using the Mentor Graphics Eldo Spice simulator and showed that the DOTB technique was working well.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2023

Mode of access: World Wide Web

ISBN: 9798480679403Subjects--Topical Terms:

649834
Electrical engineering.
Subjects--Index Terms:

Charge pumpIndex Terms--Genre/Form:

542853
Electronic books.

Integration of a Dynamic Offset Testbench in 0.18UM CMOS to Measure Comparator Offsets.
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500 $a Source: Masters Abstracts International, Volume: 83-05.
500 $a Advisor: Heedley, Perry L.
502 $a Thesis (M.Sc.)--California State University, Sacramento, 2021.
504 $a Includes bibliographical references
520 $a The Dynamic Offset Test Bench (DOTB) is a simulation technique that yields values for the input-referred offset voltage of latching comparators including both static and dynamic effects [2]. This project focuses on an implementation of the DOTB in a 0.18um CMOS silicon integrated circuit. This chip will provide a test vehicle to compare the measured performance of multiple comparators to their simulated performance. Such comparisons will help to validate the DOTB simulation technique and will provide insights into the operation of latching comparators.The comparators to be tested comprise an array of 16 comparators incorporating various intentional imperfections. A separate comparator is also included on chip to allow the DC bias voltages inside the comparator to be measured. It should be noted that the comparator and charge pump circuits were previously designed by other graduate students at Sacramento State [6].This work involved the integration of the comparator array and charge pump into a complete integrated circuit test chip, as well as the design of a 4-to-16 digital decoder, the bias circuits required for the comparator, and two 16-to-1 multiplexers. The top-level design had to accommodate the overall functionality of the various test modes required.Schematics were captured using Cadence Virtuoso, and simulations were performed to verify performance across process, supply voltage, and temperature (PVT) variations using the Mentor Graphics Eldo Spice simulator and showed that the DOTB technique was working well.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2023
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 649834
650 4 $a Educational tests & measurements. $3 3168483
650 4 $a Engineering. $3 586835
653 $a Charge pump
653 $a Comparator offset
653 $a DOTB testbench
653 $a FE bias circuit
653 $a Integrator
653 $a SMC bias circuit
655 7 $a Electronic books. $2 lcsh $3 542853
690 $a 0544
690 $a 0288
690 $a 0537
710 2 $a ProQuest Information and Learning Co. $3 783688
710 2 $a California State University, Sacramento. $b Electrical Engineering. $3 3693692
773 0 $t Masters Abstracts International $g 83-05.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28492933 $z click for full text (PQDT)