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Design of Ultra-Compact and Low-Power Sub-10 Nanometer Logic Circuits with Schottky Barrier Contacts and Gate Work-Function Engineering.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design of Ultra-Compact and Low-Power Sub-10 Nanometer Logic Circuits with Schottky Barrier Contacts and Gate Work-Function Engineering./
作者:	Canan, Talha Furkan.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2022,
面頁冊數:	190 p.
附註:	Source: Dissertations Abstracts International, Volume: 84-01, Section: B.
Contained By:	Dissertations Abstracts International84-01B.
標題:	Condensed matter physics. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=29282328
ISBN:	9798802754436

Design of Ultra-Compact and Low-Power Sub-10 Nanometer Logic Circuits with Schottky Barrier Contacts and Gate Work-Function Engineering.
Canan, Talha Furkan.

Design of Ultra-Compact and Low-Power Sub-10 Nanometer Logic Circuits with Schottky Barrier Contacts and Gate Work-Function Engineering. - Ann Arbor : ProQuest Dissertations & Theses, 2022 - 190 p.

Source: Dissertations Abstracts International, Volume: 84-01, Section: B.

Thesis (Ph.D.)--Ohio University, 2022.

This item must not be sold to any third party vendors.

As modern Complementary Semiconductor Metal Oxide (CMOS) technology is approaching to the end of scaling limits projected by Moore's Law, researchers are in a constant pursuit for alternative solutions for the continuation of this trend. Although this proposition will likely require revolutionary technologies as alternatives to replace Si CMOS, the time and cost of such dramatic replacements make industry rather reluctant to accept them as immediate solutions. Thus, designers still search ways to re-optimize and further improve the current dominant CMOS devices and the integration methods, until the proposed exclusive technologies such as III-V semiconductors on silicon, 1D/2D channel materials like dichalcogenides, carbon nanotubes, graphene or single electrontransistors are fully developed. In this evolutionary approach, Schottky barrier (SB) FinFETs are excellent candidates to address the needs of the CMOS scaling in the next few nodes and provide the time and extra room needed. In this work, the SB-FinFETs areintroduced, developed and optimized for the needs of sub-10nm CMOS integration using a novel metal work-function engineering (WFE) approach that results in substantial savings in area and power, while retaining competitive performance for logic switching.Guided by the versatile WFE approach, SB-FinFETs are designed to operate as ambipolar devices with equal current drive and high ION/IOFF ratio (> 107) necessary for optimal logic switching. Use of multiple (typically up to four) work-functions in the contacts of SB-FinFETs allow for unique local (gate-level) threshold adjustments and functional (module-level) modifications to design novel ultra-compact digital circuits with only two transistors (2T). Following the proposed WFE design methodology with independent-gate SB-FinFETs, the performance improvements in sub-10nm circuits are found to be up to 50% reduction in static (NAND,NOR,XOR) gate area, 80% in transistor count at multi-input gates and reconfigurable modules. The nature and extent of area and power advantages will depend on the complexity and style of logic implementation.We propose novel compact static CMOS logic gates with a typically x5 to x10 reduction in dissipated power and x3 to x5 reduction in switching speed, resulting power-delay products (PDP) comparable to conventional p/n junction FinFET devices found in CMOS products today. Thus the proposed methodology trades speed for power and area, which is quite acceptable for sub-10nm CMOS design that suffers from the lack of both. Based on these novel gates and extended utilization of WFE, the area and power gains was further expanded to larger combinational and sequential logic circuits such as full-adders, multiplexers, latches and flip-flops.In an effort to truly explore the capabilities of WFE as applied to SB-FinFETs, ultra-compact reconfigurable logic circuits with 2T,3T and 4T were also designed. These circuits, which allow the gate function to change between multiple outcomes by use of select input(s), require insights to inner states accessible to a given 2T/3T/4T topology when work-functions are uniquely set. They result in x3 to x10 reduction in dissipated power, x2 to x15 reduction in area overhead. At the same time there is x2 to x5 reduction in switching speed, while maintaining still competitive performance in terms of PDP.Although WFE is explored in this work in the context of SB-FinFETs, the methodologies developed here can be applied to any other device technology that may benefit from judicious use of multiple metal work-functions to create more agile andcompact logic switching.

ISBN: 9798802754436Subjects--Topical Terms:

3173567
Condensed matter physics.
Subjects--Index Terms:

Schottky Barrier

Design of Ultra-Compact and Low-Power Sub-10 Nanometer Logic Circuits with Schottky Barrier Contacts and Gate Work-Function Engineering.
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