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Architecture and Compiler Support for Parallel Consistency, Coherence, and Security.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Architecture and Compiler Support for Parallel Consistency, Coherence, and Security./
作者:	Zhang, Rui.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2020,
面頁冊數:	165 p.
附註:	Source: Dissertations Abstracts International, Volume: 83-06, Section: B.
Contained By:	Dissertations Abstracts International83-06B.
標題:	Computer engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28890336
ISBN:	9798492756635

Architecture and Compiler Support for Parallel Consistency, Coherence, and Security.
Zhang, Rui.

Architecture and Compiler Support for Parallel Consistency, Coherence, and Security. - Ann Arbor : ProQuest Dissertations & Theses, 2020 - 165 p.

Source: Dissertations Abstracts International, Volume: 83-06, Section: B.

Thesis (Ph.D.)--The Ohio State University, 2020.

This item must not be sold to any third party vendors.

The widespread use of multicore processors has made parallelism a necessity for performance. However, parallelism allows programs to share physical computing resources, such as memory and processor caches, which presents challenges for computer systems to ensure correct and secure parallel executions. Specifically, these challenges include: 1) providing strong memory consistency to programs with data races while allowing best-effort progress; 2) providing data-race-free (DRF) programs with simple, efficient cache coherence; and 3) ensuring information security for programs that run in parallel.These challenges in parallel consistency, coherence, and security motivate this work. The thesis of our work is that parallel systems can get the benefits of strong consistency, simple and efficient coherence, and strong security guarantees with little performance degradation or human effort. The goal in this dissertation is to make contributions by presenting and proposing architecture and compiler support to ensure correct and secure parallelism with minimal extra costs.Modern memory models make the DRF assumption and provide strong, well-defined end-to-end memory consistency only for DRF programs. Prior work has proposed fail-stop memory consistency to provide well-defined behaviors for all programs. However, fail-stop consistency can lead to unexpected failures in the presence of data races, imperiling performance or progress. To help systems get the benefits of fail-stop memory consistency while minimizing the costs of failures, this dissertation presents a set of architectural mechanisms that provide best-effort avoidance of failures on top of systems that provide fail-stop consistency.Unlike memory consistency models, mainstream cache coherence protocols such as MESI are designed to enforce coherence for both DRF and non-DRF programs and thus are complex. Specifically, MESI requires numerous transient states, a shared directory, and support for core-to-core communication. As DRF is widely assumed by today?s language-level memory models, this dissertation explores the possibility of providing simpler cache coherence protocols under the DRF assumption and presents a simple, efficient self-invalidation-based coherence protocol that eliminates MESI?s expensive requirements. The key insights in this work lie in its novel design that has no shared ownership metadata and that uses lightweight mechanisms to avoid many unnecessary self-invalidations.The fact that programs share physical computing resources such as memory and processor caches presents not only correctness challenges but also security threats. Among such threats, particularly worrisome are cache side-channel attacks, which have been demonstrated to be potent enough to facilitate the deduction of sensitive information in realistic scenarios. To protect programs from cache side-channel attacks, we propose automatic compiler support for strong, efficient cache side-channel protection based on widely available commodity hardware transactional memory (HTM). This work consists of a set of program analysis and instrumentation techniques that detect and analyze sensitive data and code, delimit transactions, and insert code to protect sensitive data and code.By making contributions in parallel consistency, coherence, and security, this dissertation aims to address challenges that parallelism faces to ensure correct and secure executions. Our proposed architecture support for best-effort avoidance of failures provides strong consistency without the costs of consistency failures. Our proposed coherence protocol extends the design limit of cache coherence on complexity under the DRF assumption. Last but not least, our proposed techniques of automatic cache side-channel protection help developers get the benefit of secure parallelism with little human effort. Overall, this dissertation significantly advances the state of the art in parallel consistency, coherence, and security.

ISBN: 9798492756635Subjects--Topical Terms:

621879
Computer engineering.
Subjects--Index Terms:

Data-race-free

Architecture and Compiler Support for Parallel Consistency, Coherence, and Security.
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506 $a This item must not be sold to any third party vendors.
520 $a The widespread use of multicore processors has made parallelism a necessity for performance. However, parallelism allows programs to share physical computing resources, such as memory and processor caches, which presents challenges for computer systems to ensure correct and secure parallel executions. Specifically, these challenges include: 1) providing strong memory consistency to programs with data races while allowing best-effort progress; 2) providing data-race-free (DRF) programs with simple, efficient cache coherence; and 3) ensuring information security for programs that run in parallel.These challenges in parallel consistency, coherence, and security motivate this work. The thesis of our work is that parallel systems can get the benefits of strong consistency, simple and efficient coherence, and strong security guarantees with little performance degradation or human effort. The goal in this dissertation is to make contributions by presenting and proposing architecture and compiler support to ensure correct and secure parallelism with minimal extra costs.Modern memory models make the DRF assumption and provide strong, well-defined end-to-end memory consistency only for DRF programs. Prior work has proposed fail-stop memory consistency to provide well-defined behaviors for all programs. However, fail-stop consistency can lead to unexpected failures in the presence of data races, imperiling performance or progress. To help systems get the benefits of fail-stop memory consistency while minimizing the costs of failures, this dissertation presents a set of architectural mechanisms that provide best-effort avoidance of failures on top of systems that provide fail-stop consistency.Unlike memory consistency models, mainstream cache coherence protocols such as MESI are designed to enforce coherence for both DRF and non-DRF programs and thus are complex. Specifically, MESI requires numerous transient states, a shared directory, and support for core-to-core communication. As DRF is widely assumed by today?s language-level memory models, this dissertation explores the possibility of providing simpler cache coherence protocols under the DRF assumption and presents a simple, efficient self-invalidation-based coherence protocol that eliminates MESI?s expensive requirements. The key insights in this work lie in its novel design that has no shared ownership metadata and that uses lightweight mechanisms to avoid many unnecessary self-invalidations.The fact that programs share physical computing resources such as memory and processor caches presents not only correctness challenges but also security threats. Among such threats, particularly worrisome are cache side-channel attacks, which have been demonstrated to be potent enough to facilitate the deduction of sensitive information in realistic scenarios. To protect programs from cache side-channel attacks, we propose automatic compiler support for strong, efficient cache side-channel protection based on widely available commodity hardware transactional memory (HTM). This work consists of a set of program analysis and instrumentation techniques that detect and analyze sensitive data and code, delimit transactions, and insert code to protect sensitive data and code.By making contributions in parallel consistency, coherence, and security, this dissertation aims to address challenges that parallelism faces to ensure correct and secure executions. Our proposed architecture support for best-effort avoidance of failures provides strong consistency without the costs of consistency failures. Our proposed coherence protocol extends the design limit of cache coherence on complexity under the DRF assumption. Last but not least, our proposed techniques of automatic cache side-channel protection help developers get the benefit of secure parallelism with little human effort. Overall, this dissertation significantly advances the state of the art in parallel consistency, coherence, and security.
590 $a School code: 0168.
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710 2 $a The Ohio State University. $b Computer Science and Engineering. $3 1674144
773 0 $t Dissertations Abstracts International $g 83-06B.
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792 $a 2020
793 $a English
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