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Enhancing Performance of SiC Planar-Gate Power Mosfets with 650 V, 1.2 kV, and 2.3 kV Blocking Voltages with Structural Modifications.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Enhancing Performance of SiC Planar-Gate Power Mosfets with 650 V, 1.2 kV, and 2.3 kV Blocking Voltages with Structural Modifications./
作者:	Agarwal, Aditi.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2021,
面頁冊數:	156 p.
附註:	Source: Dissertations Abstracts International, Volume: 83-04, Section: B.
Contained By:	Dissertations Abstracts International83-04B.
標題:	Electrons. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28688471
ISBN:	9798544208709

Enhancing Performance of SiC Planar-Gate Power Mosfets with 650 V, 1.2 kV, and 2.3 kV Blocking Voltages with Structural Modifications.
Agarwal, Aditi.

Enhancing Performance of SiC Planar-Gate Power Mosfets with 650 V, 1.2 kV, and 2.3 kV Blocking Voltages with Structural Modifications. - Ann Arbor : ProQuest Dissertations & Theses, 2021 - 156 p.

Source: Dissertations Abstracts International, Volume: 83-04, Section: B.

Thesis (Ph.D.)--North Carolina State University, 2021.

This item must not be sold to any third party vendors.

4H-SiC is a wide band gap material widely used for fabricating high efficiency power devices. The commercial SiC market is expected to grow five-fold by 2025. It is therefore imperative to innovate, optimize and fabricate new SiC power device structures.In this research, structural enhancements for SiC planar-gate power devices with 650 V, 1.2 kV and 2.3 kV blocking voltage capabilities have been studied experimentally and via numerical simulations. Several techniques to improve power device performance have been discussed.It has been demonstrated that reducing the gate oxide thickness to 27 nm allows reduction in device specific on-resistance without affecting the gate-drain capacitance/gate-drain charge. It is also shown that it is possible to enhance the short-circuit capability of power devices by reducing their gate oxide thickness. Additionally, reduced gate oxide devices can be driven at much lower gate voltages (10 V, 15 V) compared to the conventional 50 nm devices that are usually operated at 20 V.Silicon industry has long been driven to smaller technology nodes to improve device performance. Similarly, reducing channel length has great merit for SiC power devices. SiC MOSFETs with reduced channel length of 0.3 µm have been fabricated in this work using a non-self-aligned process. It has been shown via experiments and numerical simulations that this channel length is sufficient to prevent reach-through and high leakage current through the device. These devices have also been demonstrated to possess better high-frequency figures-of-merit and switching characteristics.Another technique to improve high-frequency figures-of-merit for a power device is to use an optimized octagonal cell topology. Octagonal cell topology has reduced gate-drain overlap due to its lower JFET density owing to device geometry.The impact of gate oxide thickness, channel length and cell topology have been studied in this work on electrical performance of 650 V, 1.2 k and 2.3 kV planar-gate power devices. Numerical analyses are presented for each device type, along with wafer-level static measurement results. Additionally, high temperature wafer-level measurements, switching waveforms and shortcircuit measurements are also reported for selected devices. Datasheet values for state-of-the-art commercial devices are presented for each voltage level for reference. Finally, comparisons are drawn between fabricated devices of each voltage class and major accomplishments of this work are reported.

ISBN: 9798544208709Subjects--Topical Terms:

516581
Electrons.

Enhancing Performance of SiC Planar-Gate Power Mosfets with 650 V, 1.2 kV, and 2.3 kV Blocking Voltages with Structural Modifications.
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520 $a 4H-SiC is a wide band gap material widely used for fabricating high efficiency power devices. The commercial SiC market is expected to grow five-fold by 2025. It is therefore imperative to innovate, optimize and fabricate new SiC power device structures.In this research, structural enhancements for SiC planar-gate power devices with 650 V, 1.2 kV and 2.3 kV blocking voltage capabilities have been studied experimentally and via numerical simulations. Several techniques to improve power device performance have been discussed.It has been demonstrated that reducing the gate oxide thickness to 27 nm allows reduction in device specific on-resistance without affecting the gate-drain capacitance/gate-drain charge. It is also shown that it is possible to enhance the short-circuit capability of power devices by reducing their gate oxide thickness. Additionally, reduced gate oxide devices can be driven at much lower gate voltages (10 V, 15 V) compared to the conventional 50 nm devices that are usually operated at 20 V.Silicon industry has long been driven to smaller technology nodes to improve device performance. Similarly, reducing channel length has great merit for SiC power devices. SiC MOSFETs with reduced channel length of 0.3 µm have been fabricated in this work using a non-self-aligned process. It has been shown via experiments and numerical simulations that this channel length is sufficient to prevent reach-through and high leakage current through the device. These devices have also been demonstrated to possess better high-frequency figures-of-merit and switching characteristics.Another technique to improve high-frequency figures-of-merit for a power device is to use an optimized octagonal cell topology. Octagonal cell topology has reduced gate-drain overlap due to its lower JFET density owing to device geometry.The impact of gate oxide thickness, channel length and cell topology have been studied in this work on electrical performance of 650 V, 1.2 k and 2.3 kV planar-gate power devices. Numerical analyses are presented for each device type, along with wafer-level static measurement results. Additionally, high temperature wafer-level measurements, switching waveforms and shortcircuit measurements are also reported for selected devices. Datasheet values for state-of-the-art commercial devices are presented for each voltage level for reference. Finally, comparisons are drawn between fabricated devices of each voltage class and major accomplishments of this work are reported.
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