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FPGA Micro-Architecture-Code Co-Design for Low-Density Parity-Check Codes for Flash Memories.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	FPGA Micro-Architecture-Code Co-Design for Low-Density Parity-Check Codes for Flash Memories./
作者:	Nakhjavani, Reza.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2021,
面頁冊數:	127 p.
附註:	Source: Dissertations Abstracts International, Volume: 83-01, Section: B.
Contained By:	Dissertations Abstracts International83-01B.
標題:	Computer engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28416652
ISBN:	9798522944261

FPGA Micro-Architecture-Code Co-Design for Low-Density Parity-Check Codes for Flash Memories.
Nakhjavani, Reza.

FPGA Micro-Architecture-Code Co-Design for Low-Density Parity-Check Codes for Flash Memories. - Ann Arbor : ProQuest Dissertations & Theses, 2021 - 127 p.

Source: Dissertations Abstracts International, Volume: 83-01, Section: B.

Thesis (Ph.D.)--University of Toronto (Canada), 2021.

This item must not be sold to any third party vendors.

The exponential growth of digital data has led to the proliferation of cloud storage systems as well as high-capacity, low-latency storage devices such as flash memory based solid-state drives (SSDs). These advances, along with the technology shrink, have increased the error rate both at system and device level. Storage device manufacturers and service providers often promise data reliability through error control coding. This dissertation is centered around the implementation of error correcting code (ECC) in data storage. In particular, we target low-density parity-check (LDPC) codes used for device-level and erasure codes used for system-level data reliability. Due to the ever-changing ECC requirements in the storage industry, we focus on field programmable gate arrays (FPGAs), given their short design cycles. Many studies on FPGA implementation of ECC focus on improving the hardware efficiency for a certain code of interest. This thesis extends this theme by considering hardware and code performance simultaneously. With the focus on ECCs used in data storage, we demonstrate a study of hardware-code co-design through an efficient FPGA micro-architecture that strikes a trade off between hardware efficiency and code performance. To this end, we leverage the FPGA's inherent physical architecture to propose an efficient reconfigurable micro-architecture for LDPC decoders. Then, we address the limitations of ECC in flash memories and define a finite decoder design space. Finally, we propose an end-to-end solution in which we leverage machine learning techniques to design a finite alphabet iterative decoder which strikes a trade off between hardware efficiency and code performance. In a separate effort, we perform a quantitative study of erasure coding design on FPGAs. We demonstrate, through probabilistic analysis, that an efficient implementation ought to allocate more resources to the common-case, while reducing the performance target for less probable cases.

ISBN: 9798522944261Subjects--Topical Terms:

621879
Computer engineering.
Subjects--Index Terms:

Decoder

FPGA Micro-Architecture-Code Co-Design for Low-Density Parity-Check Codes for Flash Memories.
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300 $a 127 p.
500 $a Source: Dissertations Abstracts International, Volume: 83-01, Section: B.
500 $a Advisor: Zhu, Jianwen.
502 $a Thesis (Ph.D.)--University of Toronto (Canada), 2021.
506 $a This item must not be sold to any third party vendors.
520 $a The exponential growth of digital data has led to the proliferation of cloud storage systems as well as high-capacity, low-latency storage devices such as flash memory based solid-state drives (SSDs). These advances, along with the technology shrink, have increased the error rate both at system and device level. Storage device manufacturers and service providers often promise data reliability through error control coding. This dissertation is centered around the implementation of error correcting code (ECC) in data storage. In particular, we target low-density parity-check (LDPC) codes used for device-level and erasure codes used for system-level data reliability. Due to the ever-changing ECC requirements in the storage industry, we focus on field programmable gate arrays (FPGAs), given their short design cycles. Many studies on FPGA implementation of ECC focus on improving the hardware efficiency for a certain code of interest. This thesis extends this theme by considering hardware and code performance simultaneously. With the focus on ECCs used in data storage, we demonstrate a study of hardware-code co-design through an efficient FPGA micro-architecture that strikes a trade off between hardware efficiency and code performance. To this end, we leverage the FPGA's inherent physical architecture to propose an efficient reconfigurable micro-architecture for LDPC decoders. Then, we address the limitations of ECC in flash memories and define a finite decoder design space. Finally, we propose an end-to-end solution in which we leverage machine learning techniques to design a finite alphabet iterative decoder which strikes a trade off between hardware efficiency and code performance. In a separate effort, we perform a quantitative study of erasure coding design on FPGAs. We demonstrate, through probabilistic analysis, that an efficient implementation ought to allocate more resources to the common-case, while reducing the performance target for less probable cases.
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650 4 $a Computer science. $3 523869
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653 $a Error Correcting Code
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653 $a Field programmable gate arrays
653 $a Low-Density Parity-Check Codes
653 $a Micro-Architecture-Code Co-Design
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793 $a English
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