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Design for testability, debug and re...

Huhn, Sebastian.

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Design for testability, debug and reliability = next generation measures using formal techniques /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design for testability, debug and reliability/ by Sebastian Huhn, Rolf Drechsler.
其他題名:	next generation measures using formal techniques /
作者:	Huhn, Sebastian.
其他作者:	Drechsler, Rolf.
出版者:	Cham :Springer International Publishing : : 2021.,
面頁冊數:	xxi, 164 p. :ill., digital ;24 cm.
內容註:	Introduction -- Integrated Circuits -- Formal Techniques -- Embedded Compression Architecture for Test Access Ports -- Optimization SAT-based Retargeting for Embedded Compression -- Reconfigurable TAP Controllers with Embedded Compression -- Embedded Multichannel Test Compression for Low-Pin Count Test -- Enhanced Reliability using Formal Techniques -- Conclusion and Outlook.
Contained By:	Springer Nature eBook
標題:	Integrated circuits - Design and construction. -
電子資源:	https://doi.org/10.1007/978-3-030-69209-4
ISBN:	9783030692094

Design for testability, debug and reliability = next generation measures using formal techniques /
Huhn, Sebastian.

Design for testability, debug and reliabilitynext generation measures using formal techniques /[electronic resource] :by Sebastian Huhn, Rolf Drechsler. - Cham :Springer International Publishing :2021. - xxi, 164 p. :ill., digital ;24 cm.

Introduction -- Integrated Circuits -- Formal Techniques -- Embedded Compression Architecture for Test Access Ports -- Optimization SAT-based Retargeting for Embedded Compression -- Reconfigurable TAP Controllers with Embedded Compression -- Embedded Multichannel Test Compression for Low-Pin Count Test -- Enhanced Reliability using Formal Techniques -- Conclusion and Outlook.

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces. Provides readers with a combination of a comprehensive set of formal techniques covering and enhancing different aspects of the state-of-the-art design and test flow for ICs; Introduces newly developed heuristic, formal optimization-based and partition-based retargeting techniques and integrates them into a common framework; Describes fully compliant (with respect to industrial de-facto standard) measures to enhance the DFT, DFD and DFR capabilities while supporting standardized data exchange formats; Includes new measures to tackle shortcomings of existing state-of-the-art methods, including zero-defect enforcing safety-critical applications.

ISBN: 9783030692094

Standard No.: 10.1007/978-3-030-69209-4doiSubjects--Topical Terms:

658490
Integrated circuits
--Design and construction.

LC Class. No.: TK7874 / .H846 2021

Dewey Class. No.: 621.3815

Design for testability, debug and reliability = next generation measures using formal techniques /
LDR:02962nmm a2200325 a 4500 001 2239897
003 DE-He213
005 20210728140516.0
006 m d
007 cr nn 008maaau
008 211111s2021 sz s 0 eng d
020 $a 9783030692094 $q (electronic bk.)
020 $a 9783030692087 $q (paper)
024 7 $a 10.1007/978-3-030-69209-4 $2 doi
035 $a 978-3-030-69209-4
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874 $b .H846 2021
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
090 $a TK7874 $b .H898 2021
100 1 $a Huhn, Sebastian. $3 3219914
245 1 0 $a Design for testability, debug and reliability $h [electronic resource] : $b next generation measures using formal techniques / $c by Sebastian Huhn, Rolf Drechsler.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2021.
300 $a xxi, 164 p. : $b ill., digital ; $c 24 cm.
505 0 $a Introduction -- Integrated Circuits -- Formal Techniques -- Embedded Compression Architecture for Test Access Ports -- Optimization SAT-based Retargeting for Embedded Compression -- Reconfigurable TAP Controllers with Embedded Compression -- Embedded Multichannel Test Compression for Low-Pin Count Test -- Enhanced Reliability using Formal Techniques -- Conclusion and Outlook.
520 $a This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces. Provides readers with a combination of a comprehensive set of formal techniques covering and enhancing different aspects of the state-of-the-art design and test flow for ICs; Introduces newly developed heuristic, formal optimization-based and partition-based retargeting techniques and integrates them into a common framework; Describes fully compliant (with respect to industrial de-facto standard) measures to enhance the DFT, DFD and DFR capabilities while supporting standardized data exchange formats; Includes new measures to tackle shortcomings of existing state-of-the-art methods, including zero-defect enforcing safety-critical applications.
650 0 $a Integrated circuits $x Design and construction. $3 658490
650 0 $a Integrated circuits $x Testing. $3 658491
650 0 $a Debugging in computer science. $3 590474
650 0 $a Integrated circuits $x Reliability. $3 672895
650 1 4 $a Circuits and Systems. $3 896527
650 2 4 $a Processor Architectures. $3 892680
700 1 $a Drechsler, Rolf. $3 827432
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer Nature eBook
856 4 0 $u https://doi.org/10.1007/978-3-030-69209-4
950 $a Engineering (SpringerNature-11647)