東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

ASIC design and synthesis = RTL desi...

Taraate, Vaibbhav.

FindBook

Google Book

Amazon

博客來

ASIC design and synthesis = RTL design using Verilog /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	ASIC design and synthesis/ by Vaibbhav Taraate.
其他題名:	RTL design using Verilog /
作者:	Taraate, Vaibbhav.
出版者:	Singapore :Springer Singapore : : 2021.,
面頁冊數:	xxi, 330 p. :ill., digital ;24 cm.
內容註:	Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
Contained By:	Springer Nature eBook
標題:	Application-specific integrated circuits - Design. -
電子資源:	https://doi.org/10.1007/978-981-33-4642-0
ISBN:	9789813346420

ASIC design and synthesis = RTL design using Verilog /
Taraate, Vaibbhav.

ASIC design and synthesisRTL design using Verilog /[electronic resource] :by Vaibbhav Taraate. - Singapore :Springer Singapore :2021. - xxi, 330 p. :ill., digital ;24 cm.

Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

ISBN: 9789813346420

Standard No.: 10.1007/978-981-33-4642-0doiSubjects--Topical Terms:

3220634
Application-specific integrated circuits
--Design.

LC Class. No.: TK7874.6 / .T373 2021

Dewey Class. No.: 621.3815

ASIC design and synthesis = RTL design using Verilog /
LDR:02476nmm a2200325 a 4500 001 2237495
003 DE-He213
005 20210628144119.0
006 m d
007 cr nn 008maaau
008 211111s2021 si s 0 eng d
020 $a 9789813346420 $q (electronic bk.)
020 $a 9789813346413 $q (paper)
024 7 $a 10.1007/978-981-33-4642-0 $2 doi
035 $a 978-981-33-4642-0
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874.6 $b .T373 2021
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
090 $a TK7874.6 $b .T176 2021
100 1 $a Taraate, Vaibbhav. $3 2195158
245 1 0 $a ASIC design and synthesis $h [electronic resource] : $b RTL design using Verilog / $c by Vaibbhav Taraate.
260 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2021.
300 $a xxi, 330 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
520 $a This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
650 0 $a Application-specific integrated circuits $x Design. $3 3220634
650 0 $a Verilog (Computer hardware description language) $3 709274
650 1 4 $a Circuits and Systems. $3 896527
650 2 4 $a Control Structures and Microprogramming. $3 895886
650 2 4 $a Logic Design. $3 892735
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer Nature eBook
856 4 0 $u https://doi.org/10.1007/978-981-33-4642-0
950 $a Engineering (SpringerNature-11647)