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Enhanced virtual prototyping = featu...

Herdt, Vladimir.

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Enhanced virtual prototyping = featuring RISC-V case studies /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Enhanced virtual prototyping/ by Vladimir Herdt, Daniel Grosse, Rolf Drechsler.
其他題名:	featuring RISC-V case studies /
作者:	Herdt, Vladimir.
其他作者:	Grosse, Daniel.
出版者:	Cham :Springer International Publishing : : 2021.,
面頁冊數:	xxi, 247 p. :ill., digital ;24 cm.
內容註:	Introduction -- Preliminaries -- An Open-Source RISC-V Evaluation Platform -- Formal Verification of SystemC-based Designs using Symbolic Simulation -- Coverage-guided Testing for Scalable Virtual Prototype Verification -- Verification of Embedded Software Binaries using Virtual Prototypes -- Validation of Firmware-Based Power Management using Virtual Prototypes -- Register-Transfer Level Correspondence Analysis -- Conclusion -- Index.
Contained By:	Springer Nature eBook
標題:	Software prototyping. -
電子資源:	https://doi.org/10.1007/978-3-030-54828-5
ISBN:	9783030548285

Enhanced virtual prototyping = featuring RISC-V case studies /
Herdt, Vladimir.

Enhanced virtual prototypingfeaturing RISC-V case studies /[electronic resource] :by Vladimir Herdt, Daniel Grosse, Rolf Drechsler. - Cham :Springer International Publishing :2021. - xxi, 247 p. :ill., digital ;24 cm.

Introduction -- Preliminaries -- An Open-Source RISC-V Evaluation Platform -- Formal Verification of SystemC-based Designs using Symbolic Simulation -- Coverage-guided Testing for Scalable Virtual Prototype Verification -- Verification of Embedded Software Binaries using Virtual Prototypes -- Validation of Firmware-Based Power Management using Virtual Prototypes -- Register-Transfer Level Correspondence Analysis -- Conclusion -- Index.

This book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW) Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects. Provides a comprehensive set of techniques to enhance all key aspects of a Virtual Prototype (VP)-based design flow Includes automated formal verification methods and advanced coverage-guided testing techniques, tailored for SystemC-based VPs Describes efficient, coverage-guided test generation methods for VP-based functional and non-functional software (SW) analysis and verification Includes correspondence analyses to utilize information between different abstraction levels in the design flow Uses several VP and SW verification case-studies that target the modern RISC-V ISA.

ISBN: 9783030548285

Standard No.: 10.1007/978-3-030-54828-5doiSubjects--Topical Terms:

3487008
Software prototyping.

LC Class. No.: QA76.76.P77 / H47 2021

Dewey Class. No.: 005.3

Enhanced virtual prototyping = featuring RISC-V case studies /
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505 0 $a Introduction -- Preliminaries -- An Open-Source RISC-V Evaluation Platform -- Formal Verification of SystemC-based Designs using Symbolic Simulation -- Coverage-guided Testing for Scalable Virtual Prototype Verification -- Verification of Embedded Software Binaries using Virtual Prototypes -- Validation of Firmware-Based Power Management using Virtual Prototypes -- Register-Transfer Level Correspondence Analysis -- Conclusion -- Index.
520 $a This book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW) Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects. Provides a comprehensive set of techniques to enhance all key aspects of a Virtual Prototype (VP)-based design flow Includes automated formal verification methods and advanced coverage-guided testing techniques, tailored for SystemC-based VPs Describes efficient, coverage-guided test generation methods for VP-based functional and non-functional software (SW) analysis and verification Includes correspondence analyses to utilize information between different abstraction levels in the design flow Uses several VP and SW verification case-studies that target the modern RISC-V ISA.
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