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Languages, design methods, and tools...

Kazmierski, Tom J.

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Languages, design methods, and tools for electronic system design = selected contributions from FDL 2018 /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Languages, design methods, and tools for electronic system design/ edited by Tom J. Kazmierski, Sebastian Steinhorst, Daniel GroBe.
其他題名:	selected contributions from FDL 2018 /
其他作者:	Kazmierski, Tom J.
出版者:	Cham :Springer international Publishing : : 2020.,
面頁冊數:	vii, 192 p. :ill., digital ;24 cm.
內容註:	introduction -- Automatic Generation of Cycle-Accurate Simulink Blocks from HDL iPs -- Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach -- Symbolic Simulation of Dataflow Synchronous Programs with Timers -- Language and Hardware Acceleration Backend for Graph Processing -- Runtime Task Mapping for Lifetime Budgeting in Many-Core Systems -- Fault Analysis in Analog Circuits through Language Manipulation and Abstraction -- Towards Consistency Checking Between HDL and UPF Descriptions.
Contained By:	Springer eBooks
標題:	Formal methods (Computer science) - Congresses. -
電子資源:	https://doi.org/10.1007/978-3-030-31585-6
ISBN:	9783030315856

Languages, design methods, and tools for electronic system design = selected contributions from FDL 2018 /
Languages, design methods, and tools for electronic system designselected contributions from FDL 2018 /[electronic resource] :edited by Tom J. Kazmierski, Sebastian Steinhorst, Daniel GroBe. - Cham :Springer international Publishing :2020. - vii, 192 p. :ill., digital ;24 cm. - Lecture notes in electrical engineering,v.6111876-1100 ;. - Lecture notes in electrical engineering ;v.611..

introduction -- Automatic Generation of Cycle-Accurate Simulink Blocks from HDL iPs -- Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach -- Symbolic Simulation of Dataflow Synchronous Programs with Timers -- Language and Hardware Acceleration Backend for Graph Processing -- Runtime Task Mapping for Lifetime Budgeting in Many-Core Systems -- Fault Analysis in Analog Circuits through Language Manipulation and Abstraction -- Towards Consistency Checking Between HDL and UPF Descriptions.

This book brings together a selection of the best papers from the twenty-first edition of the Forum on specification and Design Languages Conference (FDL), which took place on September 10-12, 2018, in Munich, Germany. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. Covers Assertion Based Design, Verification & Debug; includes language-based modeling and design techniques for embedded systems; Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains; includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE)

ISBN: 9783030315856

Standard No.: 10.1007/978-3-030-31585-6doiSubjects--Topical Terms:

622707
Formal methods (Computer science)
--Congresses.

LC Class. No.: QA76.9.F67 / L364 2020

Dewey Class. No.: 004.0151

Languages, design methods, and tools for electronic system design = selected contributions from FDL 2018 /
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