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System-on-chip security = validation...

Farahmandi, Farimah.

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System-on-chip security = validation and verification /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	System-on-chip security/ by Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra.
其他題名:	validation and verification /
作者:	Farahmandi, Farimah.
其他作者:	Huang, Yuanwen.
出版者:	Cham :Springer International Publishing : : 2020.,
面頁冊數:	xix, 289 p. :ill. (some col.), digital ;24 cm.
內容註:	Introduction -- Security Verification Using Formal Methods -- Simulation-Based Security Validation Approaches -- Security Validation Using Side-Channel Analysis -- Automated Vulnerability Detection And Mitigation -- Conclusion.
Contained By:	Springer eBooks
標題:	Systems on a chip - Security measures. -
電子資源:	https://doi.org/10.1007/978-3-030-30596-3
ISBN:	9783030305963

System-on-chip security = validation and verification /
Farahmandi, Farimah.

System-on-chip securityvalidation and verification /[electronic resource] :by Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra. - Cham :Springer International Publishing :2020. - xix, 289 p. :ill. (some col.), digital ;24 cm.

Introduction -- Security Verification Using Formal Methods -- Simulation-Based Security Validation Approaches -- Security Validation Using Side-Channel Analysis -- Automated Vulnerability Detection And Mitigation -- Conclusion.

This book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle. The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches. This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs. Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle; Summarizes unsafe current design practices that lead to security and trust vulnerabilities; Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers; Explains how to leverage security validation approaches to prevent side-channel attacks; Presents automated debugging and patching techniques in the presence of security vulnerabilities; Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs.

ISBN: 9783030305963

Standard No.: 10.1007/978-3-030-30596-3doiSubjects--Topical Terms:

3380770
Systems on a chip
--Security measures.

LC Class. No.: TK7895.E42 / F373 2020

Dewey Class. No.: 006.22

System-on-chip security = validation and verification /
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