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In-memory computing = synthesis and ...

Shirinzadeh, Saeideh.

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In-memory computing = synthesis and optimization /

Record Type:	Electronic resources : Monograph/item
Title/Author:	In-memory computing/ by Saeideh Shirinzadeh, Rolf Drechsler.
Reminder of title:	synthesis and optimization /
Author:	Shirinzadeh, Saeideh.
other author:	Drechsler, Rolf.
Published:	Cham :Springer International Publishing : : 2020.,
Description:	xi, 115 p. :ill., digital ;24 cm.
[NT 15003449]:	Chapter 1: Introduction -- Chapter 2: Background -- Chapter 3: BDD Optimization and Approximation: A Multi-Criteria Approach -- Chapter 4: Synthesis for Logic-in-Memory Computing using RRAM -- Chapter 5: Compilation and Wear Le0veling for Programmable Logic-in-Memory (PLiM) Architecture -- Chapter 6: Conclusions.
Contained By:	Springer eBooks
Subject:	Computer storage devices. -
Online resource:	https://doi.org/10.1007/978-3-030-18026-3
ISBN:	9783030180263

In-memory computing = synthesis and optimization /
Shirinzadeh, Saeideh.

In-memory computingsynthesis and optimization /[electronic resource] :by Saeideh Shirinzadeh, Rolf Drechsler. - Cham :Springer International Publishing :2020. - xi, 115 p. :ill., digital ;24 cm.

Chapter 1: Introduction -- Chapter 2: Background -- Chapter 3: BDD Optimization and Approximation: A Multi-Criteria Approach -- Chapter 4: Synthesis for Logic-in-Memory Computing using RRAM -- Chapter 5: Compilation and Wear Le0veling for Programmable Logic-in-Memory (PLiM) Architecture -- Chapter 6: Conclusions.

This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing; Describes automated compilation of programmable logic-in-memory computer architectures; Includes several effective optimization algorithm also applicable to classical logic synthesis; Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.

ISBN: 9783030180263

Standard No.: 10.1007/978-3-030-18026-3doiSubjects--Topical Terms:

649652
Computer storage devices.

LC Class. No.: TK7895.M4

Dewey Class. No.: 004.5

In-memory computing = synthesis and optimization /
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245 1 0 $a In-memory computing $h [electronic resource] : $b synthesis and optimization / $c by Saeideh Shirinzadeh, Rolf Drechsler.
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300 $a xi, 115 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1: Introduction -- Chapter 2: Background -- Chapter 3: BDD Optimization and Approximation: A Multi-Criteria Approach -- Chapter 4: Synthesis for Logic-in-Memory Computing using RRAM -- Chapter 5: Compilation and Wear Le0veling for Programmable Logic-in-Memory (PLiM) Architecture -- Chapter 6: Conclusions.
520 $a This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing; Describes automated compilation of programmable logic-in-memory computer architectures; Includes several effective optimization algorithm also applicable to classical logic synthesis; Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.
650 0 $a Computer storage devices. $3 649652
650 0 $a Nonvolatile random-access memory. $3 2062712
650 1 4 $a Circuits and Systems. $3 896527
650 2 4 $a Processor Architectures. $3 892680
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 893838
700 1 $a Drechsler, Rolf. $3 827432
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856 4 0 $u https://doi.org/10.1007/978-3-030-18026-3
950 $a Engineering (Springer-11647)