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Efficient Track-and-Hold Techniques ...

Wang, Xiao.

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Efficient Track-and-Hold Techniques for High Speed Time-interleaved ADCs.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Efficient Track-and-Hold Techniques for High Speed Time-interleaved ADCs./
作者:	Wang, Xiao.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2018,
面頁冊數:	94 p.
附註:	Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B.
Contained By:	Dissertation Abstracts International79-10B(E).
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10826681
ISBN:	9780438029507

Efficient Track-and-Hold Techniques for High Speed Time-interleaved ADCs.
Wang, Xiao.

Efficient Track-and-Hold Techniques for High Speed Time-interleaved ADCs. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 94 p.

Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B.

Thesis (Ph.D.)--University of California, Los Angeles, 2018.

Time-Interleaving (TI) can relax the power-speed tradeoffs of analog-to-digital converter (ADC) and reduce their metastability error rate while it is not free. Track-and-hold (T&H;) nonlinearity, noise and power are the main limitations of high-speed high-resolution and low-power ADCs. This dissertation introduces two efficient T&H; design techniques to improve the performances of TI-ADCs without sophisticated calibrations. Two fabricated chips with 8b 2GS/s and 8b 8.8GS/s will be shown as the silicon verification of the proposed methods.

ISBN: 9780438029507Subjects--Topical Terms:

649834
Electrical engineering.

Efficient Track-and-Hold Techniques for High Speed Time-interleaved ADCs.
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520 $a Time-Interleaving (TI) can relax the power-speed tradeoffs of analog-to-digital converter (ADC) and reduce their metastability error rate while it is not free. Track-and-hold (T&H;) nonlinearity, noise and power are the main limitations of high-speed high-resolution and low-power ADCs. This dissertation introduces two efficient T&H; design techniques to improve the performances of TI-ADCs without sophisticated calibrations. Two fabricated chips with 8b 2GS/s and 8b 8.8GS/s will be shown as the silicon verification of the proposed methods.
520 $a Two prototype ICs were designed during this work. First, a two-way time-interleaved pipelined ADC architecture was built upon a new concept of virtual-ground sampling, featuring merged front-end T/H, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the THD, bandwidth, and sample rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in a 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency. Second, a complementary dual-loop-assisted track-and-hold buffer is introduced to achieve both high linearity and bandwidth with low power. The prototype ADC also employs a two-level 2x8 master-slave hierarchical interleaved architecture and achieved an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. It achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.
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