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Novel Multicarrier Memory Channel Ar...

Bensalem, Brahim.

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Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall./
Author:	Bensalem, Brahim.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2018,
Description:	159 p.
Notes:	Source: Dissertation Abstracts International, Volume: 79-09(E), Section: B.
Contained By:	Dissertation Abstracts International79-09B(E).
Subject:	Electrical engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10793989
ISBN:	9780355909586

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall.
Bensalem, Brahim.

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 159 p.

Source: Dissertation Abstracts International, Volume: 79-09(E), Section: B.

Thesis (Ph.D.)--Arizona State University, 2018.

The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.

ISBN: 9780355909586Subjects--Topical Terms:

649834
Electrical engineering.

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall.
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100 1 $a Bensalem, Brahim. $3 3427794
245 1 0 $a Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2018
300 $a 159 p.
500 $a Source: Dissertation Abstracts International, Volume: 79-09(E), Section: B.
500 $a Adviser: James T. Aberle.
502 $a Thesis (Ph.D.)--Arizona State University, 2018.
520 $a The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
520 $a A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink(TM) and demonstrated the MCMCA performance for ultra-high throughput memory channel.
520 $a Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
590 $a School code: 0010.
650 4 $a Electrical engineering. $3 649834
650 4 $a Electromagnetics. $3 3173223
650 4 $a Engineering. $3 586835
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710 2 $a Arizona State University. $b Electrical Engineering. $3 1671741
773 0 $t Dissertation Abstracts International $g 79-09B(E).
790 $a 0010
791 $a Ph.D.
792 $a 2018
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10793989