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Investigation on SiGe selective epit...

Wang, Guilei.

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Investigation on SiGe selective epitaxy for source and drain engineering in 22 nm CMOS technology node and beyond

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Investigation on SiGe selective epitaxy for source and drain engineering in 22 nm CMOS technology node and beyond/ by Guilei Wang.
作者:	Wang, Guilei.
出版者:	Singapore :Springer Singapore : : 2019.,
面頁冊數:	xvi, 115 p. :ill., digital ;24 cm.
內容註:	Introduction -- Strain technology of Si-based materials -- SiGe Epitaxial Growth and material characterization -- SiGe Source and Drain Integration and transistor performance investigation -- Pattern Dependency behavior of SiGe Selective Epitaxy -- Summary and final words.
Contained By:	Springer eBooks
標題:	Epitaxy. -
電子資源:	https://doi.org/10.1007/978-981-15-0046-6
ISBN:	9789811500466

Investigation on SiGe selective epitaxy for source and drain engineering in 22 nm CMOS technology node and beyond
Wang, Guilei.

Investigation on SiGe selective epitaxy for source and drain engineering in 22 nm CMOS technology node and beyond[electronic resource] /by Guilei Wang. - Singapore :Springer Singapore :2019. - xvi, 115 p. :ill., digital ;24 cm. - Springer theses,2190-5053. - Springer theses..

Introduction -- Strain technology of Si-based materials -- SiGe Epitaxial Growth and material characterization -- SiGe Source and Drain Integration and transistor performance investigation -- Pattern Dependency behavior of SiGe Selective Epitaxy -- Summary and final words.

This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling. As the CMOS technology roadmap calls for continuously downscaling traditional transistor structures, controlling the parasitic effects of transistors, e.g. short channel effect, parasitic resistances and capacitances is becoming increasingly difficult. The emergence of these problems sparked a technological revolution, where a transition from planar to three-dimensional (3D) transistor design occurred in the 22nm technology node. The selective epitaxial growth (SEG) method has been used to deposit SiGe as stressor material in S/D regions to induce uniaxial strain in the channel region. The thesis investigates issues of process integration in IC production and concentrates on the key parameters of high-quality SiGe selective epitaxial growth, with a special focus on its pattern dependency behavior and on key integration issues in both 2D and 3D transistor structures, the goal being to improve future applications of SiGe SEG in advanced CMOS.

ISBN: 9789811500466

Standard No.: 10.1007/978-981-15-0046-6doiSubjects--Topical Terms:

584860
Epitaxy.

LC Class. No.: QD921 / .W364 2020

Dewey Class. No.: 548.5

Investigation on SiGe selective epitaxy for source and drain engineering in 22 nm CMOS technology node and beyond
LDR:02454nmm a2200337 a 4500 001 2193378
003 DE-He213
005 20191224112931.0
006 m d
007 cr nn 008maaau
008 200514s2019 si s 0 eng d
020 $a 9789811500466 $q (electronic bk.)
020 $a 9789811500459 $q (paper)
024 7 $a 10.1007/978-981-15-0046-6 $2 doi
035 $a 978-981-15-0046-6
040 $a GP $c GP
041 0 $a eng
050 4 $a QD921 $b .W364 2020
072 7 $a TJFD5 $2 bicssc
072 7 $a TEC008090 $2 bisacsh
072 7 $a TJFD $2 thema
082 0 4 $a 548.5 $2 23
090 $a QD921 $b .W246 2020
100 1 $a Wang, Guilei. $3 3414504
245 1 0 $a Investigation on SiGe selective epitaxy for source and drain engineering in 22 nm CMOS technology node and beyond $h [electronic resource] / $c by Guilei Wang.
260 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2019.
300 $a xvi, 115 p. : $b ill., digital ; $c 24 cm.
490 1 $a Springer theses, $x 2190-5053
505 0 $a Introduction -- Strain technology of Si-based materials -- SiGe Epitaxial Growth and material characterization -- SiGe Source and Drain Integration and transistor performance investigation -- Pattern Dependency behavior of SiGe Selective Epitaxy -- Summary and final words.
520 $a This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling. As the CMOS technology roadmap calls for continuously downscaling traditional transistor structures, controlling the parasitic effects of transistors, e.g. short channel effect, parasitic resistances and capacitances is becoming increasingly difficult. The emergence of these problems sparked a technological revolution, where a transition from planar to three-dimensional (3D) transistor design occurred in the 22nm technology node. The selective epitaxial growth (SEG) method has been used to deposit SiGe as stressor material in S/D regions to induce uniaxial strain in the channel region. The thesis investigates issues of process integration in IC production and concentrates on the key parameters of high-quality SiGe selective epitaxial growth, with a special focus on its pattern dependency behavior and on key integration issues in both 2D and 3D transistor structures, the goal being to improve future applications of SiGe SEG in advanced CMOS.
650 0 $a Epitaxy. $3 584860
650 0 $a Metal oxide semiconductors, Complementary $x Materials. $3 3414505
650 1 4 $a Semiconductors. $3 516162
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Nanotechnology and Microengineering. $3 1005737
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
830 0 $a Springer theses. $3 1314442
856 4 0 $u https://doi.org/10.1007/978-981-15-0046-6
950 $a Physics and Astronomy (Springer-11651)