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Quilt packaging: A novel high speed ...

Liu, Qing.

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Quilt packaging: A novel high speed chip -to -chip communication paradigm for system -in -package.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Quilt packaging: A novel high speed chip -to -chip communication paradigm for system -in -package./
作者:	Liu, Qing.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2008,
面頁冊數:	213 p.
附註:	Source: Dissertation Abstracts International, Volume: 69-01, Section: B, page: 5560.
Contained By:	Dissertation Abstracts International69-01B.
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3299159
ISBN:	9780549434641

Quilt packaging: A novel high speed chip -to -chip communication paradigm for system -in -package.
Liu, Qing.

Quilt packaging: A novel high speed chip -to -chip communication paradigm for system -in -package. - Ann Arbor : ProQuest Dissertations & Theses, 2008 - 213 p.

Source: Dissertation Abstracts International, Volume: 69-01, Section: B, page: 5560.

Thesis (Ph.D.)--University of Notre Dame, 2008.

As state-of-the-art transistor features continue to shrink and the incorporation of high-k, low-k isolation dielectric materials and strained and SiGe layers on silicon becomes common, chip density and performance are improved. However, system performance has not kept up with the pace especially at multi-GHz clock rates. The bottleneck is packaging. Conventional packaging techniques require high driving current and large in-die area for bonding pads, and provide limited bandwidth. As a result, several technologies, such as system-on-chip, system-in-packaging and system-on-packaging, have been actively pursed to meet the demands of low power, high I/O counts and fast chip-to-chip communication. Here, we present a novel packaging technique, Quilt Packaging (QP), for system-in-package. QP uses microelectromechanical systems (MEMS) inspired fabrication techniques to form contacts along the vertical edge facets of the integrated circuits (ICs) during the back-end-of-line process, enabling the ICs to be interconnected by butting them against each other. A shorter path between chips is established compared with other system-in-packaging techniques pursued by industry, which leads to shorter delay, less power consumption and better signal integrity. The contacts are formed by copper nodules embedded inside the silicon substrate. Nodules are made of trenches into the silicon substrate by deep reactive ion etch (DRIE), which are filled by electrolytic copper plating followed by chemical-mechanical polishing (CMP). Different QP structures are fabricated with nodule depth of 20 mum and widths from 10 mum to 100 mum. To further improve the transmission performance, tapered nodules, which provide better impedance matching to on-chip interconnects, are designed and fabricated.

ISBN: 9780549434641Subjects--Topical Terms:

649834
Electrical engineering.

Quilt packaging: A novel high speed chip -to -chip communication paradigm for system -in -package.
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300 $a 213 p.
500 $a Source: Dissertation Abstracts International, Volume: 69-01, Section: B, page: 5560.
500 $a Adviser: Gary H. Bernstein.
502 $a Thesis (Ph.D.)--University of Notre Dame, 2008.
520 $a As state-of-the-art transistor features continue to shrink and the incorporation of high-k, low-k isolation dielectric materials and strained and SiGe layers on silicon becomes common, chip density and performance are improved. However, system performance has not kept up with the pace especially at multi-GHz clock rates. The bottleneck is packaging. Conventional packaging techniques require high driving current and large in-die area for bonding pads, and provide limited bandwidth. As a result, several technologies, such as system-on-chip, system-in-packaging and system-on-packaging, have been actively pursed to meet the demands of low power, high I/O counts and fast chip-to-chip communication. Here, we present a novel packaging technique, Quilt Packaging (QP), for system-in-package. QP uses microelectromechanical systems (MEMS) inspired fabrication techniques to form contacts along the vertical edge facets of the integrated circuits (ICs) during the back-end-of-line process, enabling the ICs to be interconnected by butting them against each other. A shorter path between chips is established compared with other system-in-packaging techniques pursued by industry, which leads to shorter delay, less power consumption and better signal integrity. The contacts are formed by copper nodules embedded inside the silicon substrate. Nodules are made of trenches into the silicon substrate by deep reactive ion etch (DRIE), which are filled by electrolytic copper plating followed by chemical-mechanical polishing (CMP). Different QP structures are fabricated with nodule depth of 20 mum and widths from 10 mum to 100 mum. To further improve the transmission performance, tapered nodules, which provide better impedance matching to on-chip interconnects, are designed and fabricated.
520 $a QP is a novel packaging technique for ultra-fast and low-power chip-to-chip communications. The fabrication process of QP can be easily integrated into standard IC process with an extra two masks, one for the nodules and the other for the separation of the chips. The system performance by implementing QP can be dramatically improved along with the improvement of the ICs trends.
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