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Novel Structures for High-Speed Delt...

Chae, Jeong Seok.

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Novel Structures for High-Speed Delta-Sigma Data Converters.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Novel Structures for High-Speed Delta-Sigma Data Converters./
作者:	Chae, Jeong Seok.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2011,
面頁冊數:	102 p.
附註:	Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3611.
Contained By:	Dissertation Abstracts International72-06B.
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3452544
ISBN:	9781124596242

Novel Structures for High-Speed Delta-Sigma Data Converters.
Chae, Jeong Seok.

Novel Structures for High-Speed Delta-Sigma Data Converters. - Ann Arbor : ProQuest Dissertations & Theses, 2011 - 102 p.

Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3611.

Thesis (Ph.D.)--Oregon State University, 2011.

This item is not available from ProQuest Dissertations & Theses.

As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital blocks, which can process audio to communication data. Nowadays, wideband and low-power data converter is mandatory for mobile applications which need a bridge between analog and digital blocks.

ISBN: 9781124596242Subjects--Topical Terms:

649834
Electrical engineering.

Novel Structures for High-Speed Delta-Sigma Data Converters.
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245 1 0 $a Novel Structures for High-Speed Delta-Sigma Data Converters.
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300 $a 102 p.
500 $a Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3611.
500 $a Adviser: Gabor C. Temes.
502 $a Thesis (Ph.D.)--Oregon State University, 2011.
506 $a This item is not available from ProQuest Dissertations & Theses.
520 $a As CMOS processes keep scaling down devices, the maximum operating frequencies of CMOS devices increase, and hence circuits can process very wide band signals. Moreover, the small physical dimensions of transistors allow the placing of many more blocks into a single chip, including highly accurate analog blocks and complicated digital blocks, which can process audio to communication data. Nowadays, wideband and low-power data converter is mandatory for mobile applications which need a bridge between analog and digital blocks.
520 $a In this dissertation, low-power and wideband techniques are proposed. An embedded-adder quantizer with dynamic preamplifier is proposed to achieve power-efficient operation. Various double-sampling schemes are studied, and novel schemes are presented to achieve wideband operation without noise folding effect. To reduce timing delay and idle tones, a high speed DEM which alternates two sets of comparator references is proposed. Multi-cell architecture is studied to insure higher performance when the number of modulators increases.
520 $a 0.18 mm double-poly/4-metal CMOS process was used to implement a prototype IC. 20 MHz signal bandwidth was achieved with a 320 MHz sampling clock. The peak SNDR was 63 dB. The figure-of-merit FoM = P/(2*BW*2ENOB) was 0.35 pJ/conversion, with a 16 mW power consumption. Measurement results show that the proposed design ideas are useful for low-power and wideband delta-sigma modulators which have low OSR.
520 $a A second-order noise-coupled modulator with an embedded-zero optimization was proposed to reduce power consumption by eliminating some of the integrators. This architecture makes easier the implementation of the small feedback capacitors for high OSR modulators.
590 $a School code: 0172.
650 4 $a Electrical engineering. $3 649834
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710 2 $a Oregon State University. $3 625720
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793 $a English
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