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Efficient and verifiable timing chan...

Wang, Yao.

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Efficient and verifiable timing channel protection for multi-core processors.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Efficient and verifiable timing channel protection for multi-core processors./
作者:	Wang, Yao.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2017,
面頁冊數:	205 p.
附註:	Source: Dissertation Abstracts International, Volume: 78-06(E), Section: B.
Contained By:	Dissertation Abstracts International78-06B(E).
標題:	Computer engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10253735
ISBN:	9781369560985

Efficient and verifiable timing channel protection for multi-core processors.
Wang, Yao.

Efficient and verifiable timing channel protection for multi-core processors. - Ann Arbor : ProQuest Dissertations & Theses, 2017 - 205 p.

Source: Dissertation Abstracts International, Volume: 78-06(E), Section: B.

Thesis (Ph.D.)--Cornell University, 2017.

Modern computing systems are becoming increasingly vulnerable to timing.

ISBN: 9781369560985Subjects--Topical Terms:

621879
Computer engineering.

Efficient and verifiable timing channel protection for multi-core processors.
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245 1 0 $a Efficient and verifiable timing channel protection for multi-core processors.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2017
300 $a 205 p.
500 $a Source: Dissertation Abstracts International, Volume: 78-06(E), Section: B.
500 $a Adviser: Edward Suh.
502 $a Thesis (Ph.D.)--Cornell University, 2017.
520 $a Modern computing systems are becoming increasingly vulnerable to timing.
520 $a channel attacks that leak confidential information through the timing of.
520 $a microarchitectural events. Many timing channel attacks are caused.
520 $a by the interference between different programs in the shared resources.
520 $a of a multi-core processor. For example, an attacker program's cache lines.
520 $a can be evicted by a victim program, which allows the attacker to infer.
520 $a secret information about the victim. Timing channel attacks pose serious.
520 $a threats to contemporary computing systems because they can bypass.
520 $a traditional defense mechanisms such as access control. Previous.
520 $a studies have even demonstrated a practical timing channel attack to recover.
520 $a the keystrokes of a user in the commercial Amazon EC2 cloud.
520 $a In this thesis, we explored new timing channel attacks and developed timing.
520 $a channel protection schemes for some of the hardware resources in a multi-core.
520 $a processor. Specifically, we discovered new timing channel attacks in the.
520 $a shared on-chip networks and memory controllers. We proposed multiple.
520 $a protection mechanisms for on-chip networks, caches and memory controllers.
520 $a Our protection schemes cover three high-level approaches: bi-directional.
520 $a protections, uni-directional protections and protections that trade off.
520 $a security for performance. We evaluate our protection schemes and.
520 $a show that the proposed schemes are effective against timing channel attacks.
520 $a while achieving performance improvements over previous protection schemes.
520 $a Finally, we implemented some of the protection mechanisms in RTL and used.
520 $a SecVerilog to verify the information flow control in hardware. The results.
520 $a show that the protection mechanisms indeed remove timing channels at the.
520 $a gate level.
590 $a School code: 0058.
650 4 $a Computer engineering. $3 621879
650 4 $a Computer science. $3 523869
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710 2 $a Cornell University. $b Electrical & Computer Engrng. $3 3284554
773 0 $t Dissertation Abstracts International $g 78-06B(E).
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791 $a Ph.D.
792 $a 2017
793 $a English
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