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NAND flash memory: Characterization,...

Cai, Yu.

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NAND flash memory: Characterization, analysis, modelling, and mechanisms.

Record Type:	Electronic resources : Monograph/item
Title/Author:	NAND flash memory: Characterization, analysis, modelling, and mechanisms./
Author:	Cai, Yu.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2012,
Description:	143 p.
Notes:	Source: Dissertation Abstracts International, Volume: 74-12(E), Section: B.
Contained By:	Dissertation Abstracts International74-12B(E).
Subject:	Computer engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3573487
ISBN:	9781303436789

NAND flash memory: Characterization, analysis, modelling, and mechanisms.
Cai, Yu.

NAND flash memory: Characterization, analysis, modelling, and mechanisms. - Ann Arbor : ProQuest Dissertations & Theses, 2012 - 143 p.

Source: Dissertation Abstracts International, Volume: 74-12(E), Section: B.

Thesis (Ph.D.)--Carnegie Mellon University, 2012.

This item is not available from ProQuest Dissertations & Theses.

NAND flash memory has been widely used for data storage due to its high density, high throughput, low cost, and low power. However, as flash memory manufacturers scale to smaller process technologies and store more bits per cell, the reliability and endurance of flash memory are decreasing. Various fault tolerant mechanisms, such as wear-leveling and error correction coding etc, can significantly improve both reliability and endurance of NAND flash, but finding effective algorithms requires quick and accurate characterization of flash memory error patterns.

ISBN: 9781303436789Subjects--Topical Terms:

621879
Computer engineering.

NAND flash memory: Characterization, analysis, modelling, and mechanisms.
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020 $a 9781303436789
035 $a (MiAaPQ)AAI3573487
035 $a AAI3573487
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100 1 $a Cai, Yu. $3 1272684
245 1 0 $a NAND flash memory: Characterization, analysis, modelling, and mechanisms.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2012
300 $a 143 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-12(E), Section: B.
500 $a Adviser: Ken Mai.
502 $a Thesis (Ph.D.)--Carnegie Mellon University, 2012.
506 $a This item is not available from ProQuest Dissertations & Theses.
520 $a NAND flash memory has been widely used for data storage due to its high density, high throughput, low cost, and low power. However, as flash memory manufacturers scale to smaller process technologies and store more bits per cell, the reliability and endurance of flash memory are decreasing. Various fault tolerant mechanisms, such as wear-leveling and error correction coding etc, can significantly improve both reliability and endurance of NAND flash, but finding effective algorithms requires quick and accurate characterization of flash memory error patterns.
520 $a To this end, we have designed and implemented an FPGA-based open framework for quick, accurate, and comprehensive characterization of flash memories throughout its lifetime. This dissertation first examines the complex NAND flash errors that occur at 30-40nm flash technologies, which is read in hard bits. We demonstrate distinct error patterns, such as cycle-dependency, location-dependency and value-dependency, for various types of flash operations. We analyze the discovered error patterns and explain why they exist from a circuit and device standpoint.
520 $a Based on the error patterns, this dissertation finds that stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. To tolerate high bit error rates without requiring prohibitively strong ECC, new techniques called Flash Correct-and-Refresh (FCR) are proposed and evaluated. FCR exploits the observation that the dominant error source in NAND flash memory is retention error, caused by flash cells losing charges over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that such techniques can provide 46x average lifetime improvement on a variety of workloads at no additional hardware cost. This technique achieves lifetime improvements that cannot feasibly be achieved with just stronger ECC. Understanding, characterizing, and modeling the distribution of the threshold voltages across different cells in modern multi-level cell (MLC) flash memory can enable the design of more effective and efficient error correction mechanisms to combat this degradation. This dissertation shows the first experimental measurement-based characterization of the threshold voltage distribution of flash memory. To accomplish this, a testing infrastructure that uses the read retry feature present in some 2Y-nm (i.e., 20- 24nm) flash chips is developed. This dissertation devises a model of the threshold voltage distributions taking into account program/erase (P/E) cycle effects, analyze the noise in the distributions, and evaluate the accuracy of our model. A key result is that the threshold voltage distribution after erase/program operation can be modeled, with more than high accuracy, as a Gaussian distribution with additive white noise, which shifts to the right and widens as P/E cycles increase.
520 $a One of the most significant obstacles to continued MLC NAND flash scaling is the increasing cellto-cell program interference due to increasing parasitic capacitances between the cells' floating gates. This dissertation also characterizes the cell-to-cell program interference under various programming conditions. The program interference can be accurately modeled as additive noise following Gaussian-mixture distributions, which can be predicted with high accuracy using linear regression models. To leverage the program interference model, optimum read reference voltage prediction techniques are proposed that can reduce the raw flash BER by 64% and increases the flash lifetime by 30%.
520 $a The novel characterization and models provided in this paper can enable more design of effective error tolerance mechanisms such as advanced memory signal processing and soft-decoding ECC (e.g. LDPC codes) for future NAND flash memories.
590 $a School code: 0041.
650 4 $a Computer engineering. $3 621879
650 4 $a Electrical engineering. $3 649834
690 $a 0464
690 $a 0544
710 2 $a Carnegie Mellon University. $3 1018096
773 0 $t Dissertation Abstracts International $g 74-12B(E).
790 $a 0041
791 $a Ph.D.
792 $a 2012
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3573487