東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Separation logic for high-level synt...

Winterstein, Felix.

FindBook

Google Book

Amazon

博客來

Separation logic for high-level synthesis

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Separation logic for high-level synthesis/ by Felix Winterstein.
作者:	Winterstein, Felix.
出版者:	Cham :Springer International Publishing : : 2017.,
面頁冊數:	xix, 132 p. :ill., digital ;24 cm.
內容註:	1. Introduction -- 2. High-level Synthesis of Dynamic Data Structures -- 3. Background -- 4. Heap Partitioning and Parallelisation -- 5. Custom Multi-Cache Architectures -- 6. Conclusion -- Bibliography -- Appendices.
Contained By:	Springer eBooks
標題:	Parallel processing (Electronic computers) -
電子資源:	http://dx.doi.org/10.1007/978-3-319-53222-6
ISBN:	9783319532226

Separation logic for high-level synthesis
Winterstein, Felix.

Separation logic for high-level synthesis[electronic resource] /by Felix Winterstein. - Cham :Springer International Publishing :2017. - xix, 132 p. :ill., digital ;24 cm. - Springer theses,2190-5053. - Springer theses..

1. Introduction -- 2. High-level Synthesis of Dynamic Data Structures -- 3. Background -- 4. Heap Partitioning and Parallelisation -- 5. Custom Multi-Cache Architectures -- 6. Conclusion -- Bibliography -- Appendices.

ISBN: 9783319532226

Standard No.: 10.1007/978-3-319-53222-6doiSubjects--Topical Terms:

653284
Parallel processing (Electronic computers)

LC Class. No.: QA76.58

Dewey Class. No.: 004.35

Separation logic for high-level synthesis
LDR:01155nmm a2200313 a 4500 001 2090333
003 DE-He213
005 20170823155236.0
006 m d
007 cr nn 008maaau
008 171013s2017 gw s 0 eng d
020 $a 9783319532226 $q (electronic bk.)
020 $a 9783319532219 $q (paper)
024 7 $a 10.1007/978-3-319-53222-6 $2 doi
035 $a 978-3-319-53222-6
040 $a GP $c GP
041 0 $a eng
050 4 $a QA76.58
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 004.35 $2 23
090 $a QA76.58 $b .W788 2017
100 1 $a Winterstein, Felix. $3 3221778
245 1 0 $a Separation logic for high-level synthesis $h [electronic resource] / $c by Felix Winterstein.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2017.
300 $a xix, 132 p. : $b ill., digital ; $c 24 cm.
490 1 $a Springer theses, $x 2190-5053
505 0 $a 1. Introduction -- 2. High-level Synthesis of Dynamic Data Structures -- 3. Background -- 4. Heap Partitioning and Parallelisation -- 5. Custom Multi-Cache Architectures -- 6. Conclusion -- Bibliography -- Appendices.
650 0 $a Parallel processing (Electronic computers) $3 653284
650 0 $a Embedded computer systems $x Design. $3 1001793
650 1 4 $a Engineering. $3 586835
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Memory Structures. $3 898261
650 2 4 $a Logic Design. $3 892735
650 2 4 $a Programming Languages, Compilers, Interpreters. $3 891123
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
830 0 $a Springer theses. $3 1314442
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-53222-6
950 $a Engineering (Springer-11647)