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New device matching strategies for h...

Zeng, Tao.

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New device matching strategies for high-precision analog and mixed-signal circuits.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	New device matching strategies for high-precision analog and mixed-signal circuits./
作者:	Zeng, Tao.
面頁冊數:	127 p.
附註:	Source: Dissertation Abstracts International, Volume: 75-02(E), Section: B.
Contained By:	Dissertation Abstracts International75-02B(E).
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3597420
ISBN:	9781303454905

New device matching strategies for high-precision analog and mixed-signal circuits.
Zeng, Tao.

New device matching strategies for high-precision analog and mixed-signal circuits. - 127 p.

Source: Dissertation Abstracts International, Volume: 75-02(E), Section: B.

Thesis (Ph.D.)--Iowa State University, 2013.

This item must not be sold to any third party vendors.

For several decades, technology scaling has brought many orders of magnitude improvements in digital CMOS performance and similar economic benefits to consumers. Feature size is quickly approaching nanometer scale, and the associated large variability imposes grand challenges in achieving reliable and robust operation. This is especially so for high-precision analog and mixed-signal circuits since they have always relied on accurate device matching which will not be available in nanometer CMOS or emerging technologies. This dissertation is aiming to develop design methodologies for overcoming such grand challenges without the conventional matching requirements. The underlining hypothesis is that, from a population of devices with significant variability, correct interconnection and sequencing can produce an effective system level matching that is several orders of magnitude better than the original devices. The optimal solution is non-deterministic polynomial-time hard but a simple ordered element matching strategy based on ordered statistics produces dramatically improved matching. Practical implementation of the new matching strategy is demonstrated on a 15-bit binary-weighted current-steering digital-to-analog converter design in a 130nm CMOS technology. The core area of the chip is less than 0.42mm2, among which the MSB current source area is well within 0.021mm2. Measurement results have shown that the differential nonlinearity and integral nonlinearity can be reduced from 9.85LSB and 17.41LSB to 0.34LSB and 0.77LSB, respectively.

ISBN: 9781303454905Subjects--Topical Terms:

649834
Electrical engineering.

New device matching strategies for high-precision analog and mixed-signal circuits.
LDR:02569nmm a2200289 4500 001 2059939
005 20150822105424.5
008 170521s2013 ||||||||||||||||| ||eng d
020 $a 9781303454905
035 $a (MiAaPQ)AAI3597420
035 $a AAI3597420
040 $a MiAaPQ $c MiAaPQ
100 1 $a Zeng, Tao. $3 1907849
245 1 0 $a New device matching strategies for high-precision analog and mixed-signal circuits.
300 $a 127 p.
500 $a Source: Dissertation Abstracts International, Volume: 75-02(E), Section: B.
500 $a Adviser: Degang Chen Chen.
502 $a Thesis (Ph.D.)--Iowa State University, 2013.
506 $a This item must not be sold to any third party vendors.
506 $a This item must not be added to any third party search indexes.
520 $a For several decades, technology scaling has brought many orders of magnitude improvements in digital CMOS performance and similar economic benefits to consumers. Feature size is quickly approaching nanometer scale, and the associated large variability imposes grand challenges in achieving reliable and robust operation. This is especially so for high-precision analog and mixed-signal circuits since they have always relied on accurate device matching which will not be available in nanometer CMOS or emerging technologies. This dissertation is aiming to develop design methodologies for overcoming such grand challenges without the conventional matching requirements. The underlining hypothesis is that, from a population of devices with significant variability, correct interconnection and sequencing can produce an effective system level matching that is several orders of magnitude better than the original devices. The optimal solution is non-deterministic polynomial-time hard but a simple ordered element matching strategy based on ordered statistics produces dramatically improved matching. Practical implementation of the new matching strategy is demonstrated on a 15-bit binary-weighted current-steering digital-to-analog converter design in a 130nm CMOS technology. The core area of the chip is less than 0.42mm2, among which the MSB current source area is well within 0.021mm2. Measurement results have shown that the differential nonlinearity and integral nonlinearity can be reduced from 9.85LSB and 17.41LSB to 0.34LSB and 0.77LSB, respectively.
590 $a School code: 0097.
650 4 $a Electrical engineering. $3 649834
690 $a 0544
710 2 $a Iowa State University. $b Electrical and Computer Engineering. $3 1018524
773 0 $t Dissertation Abstracts International $g 75-02B(E).
790 $a 0097
791 $a Ph.D.
792 $a 2013
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3597420