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Design Techniques for Low-Power Mult...

Jiang, Tao.

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Design Techniques for Low-Power Multi-GS/s Analog-to-Digital Converters.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design Techniques for Low-Power Multi-GS/s Analog-to-Digital Converters./
作者:	Jiang, Tao.
面頁冊數:	113 p.
附註:	Source: Dissertation Abstracts International, Volume: 75-01(E), Section: B.
Contained By:	Dissertation Abstracts International75-01B(E).
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3574317
ISBN:	9781303492341

Design Techniques for Low-Power Multi-GS/s Analog-to-Digital Converters.
Jiang, Tao.

Design Techniques for Low-Power Multi-GS/s Analog-to-Digital Converters. - 113 p.

Source: Dissertation Abstracts International, Volume: 75-01(E), Section: B.

Thesis (Ph.D.)--Oregon State University, 2013.

This item must not be sold to any third party vendors.

Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off of the number of the channels and the sampling rate in each channel. Phase misalignment and channel mismatch must be considered too. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra-high frequency, and certain techniques must be taken to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed.

ISBN: 9781303492341Subjects--Topical Terms:

649834
Electrical engineering.

Design Techniques for Low-Power Multi-GS/s Analog-to-Digital Converters.
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245 1 0 $a Design Techniques for Low-Power Multi-GS/s Analog-to-Digital Converters.
300 $a 113 p.
500 $a Source: Dissertation Abstracts International, Volume: 75-01(E), Section: B.
500 $a Adviser: Patrick Chiang.
502 $a Thesis (Ph.D.)--Oregon State University, 2013.
506 $a This item must not be sold to any third party vendors.
520 $a Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off of the number of the channels and the sampling rate in each channel. Phase misalignment and channel mismatch must be considered too. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra-high frequency, and certain techniques must be taken to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed.
520 $a A single channel, asynchronous successive approximation (SA) ADC with improved feedback delay has been fabricated in 40nm CMOS. Compared with a conventional SA structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SA-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator's quantization delay, as the digital logic delay is eliminated. Measurement results of the 40nm-CMOS SA-ADC achieves peak SNDR of 32.9dB at 1GS/s and 30.5dB at 1.25GS/s, consuming 5.28mW and 6.08mW respectively, leading to FoM of 148fJ/conversion-step and 178fJ/conversion-step, in a core area less than 170microm by 85microm.
520 $a Based on the previous work of sub-ADC, a 12-GS/s 5-b 50-mW ADC is designed in 40nm CMOS with 8 time-interleaved channels of Flash-SA hybrid structure each running at 1.5GS/s. A modified bootstrapped switch is used in the track-and-hold circuit, introducing a global clock signal to synchronize the sampling instants of each individual channel, therefore improve the phase alignment and reduce distortion. The global clock is provided by a CML buffer which is injected by off-chip low-noise sine-wave signal, so that the RMS dynamic jitter is low for better ENOB performance. Measurement results show that the 12GS/s ADC can achieve a SNDR of 25.8dB with the input signal frequency around DC and 22.8dB around 2GHz, consuming 32.1mW, leading to FoM of 237.3fJ/conversion-step, in a core area less than 800microm by 500microm.
590 $a School code: 0172.
650 4 $a Electrical engineering. $3 649834
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710 2 $a Oregon State University. $b Electrical Engineering and Computer Science. $3 3174068
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