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Energy efficient hardware-software c...

Ou, Jingzhao.

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Energy efficient hardware-software co-synthesis using reconfigurable hardware

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Energy efficient hardware-software co-synthesis using reconfigurable hardware/ Jingzhao Ou, Viktor K. Prasanna.
作者:	Ou, Jingzhao.
其他作者:	Prasanna Kumar, V. K.
出版者:	Boca Raton, Fla :Chapman & Hall/CRC, : c2010.,
面頁冊數:	1 online resource (202 p.) :ill.
內容註:	Cover; Title; Copyright; Contents; List of Tables; List of Figures; Acknowledgments; Preface; Chapter 1: Introduction; Chapter 2: Reconfigurable Hardware; Chapter 3: A High-Level Hardware-Software Application Development Framework; Chapter 4: Energy Performance Modeling and Energy Efficient Mapping for a Class of Applications; Chapter 5: High-Level Rapid Energy Estimation and Design Space Exploration; Chapter 6: Hardware-Software Co-Design for Energy Efficient Implementations of Operating Systems; Chapter 7: Concluding Remarks and Future Directions; References; Index;
標題:	Field programmable gate arrays - Energy consumption. -
電子資源:	http://www.crcnetbase.com/isbn/9781584887416
ISBN:	9781584887423 (electronic bk.)

Energy efficient hardware-software co-synthesis using reconfigurable hardware
Ou, Jingzhao.

Energy efficient hardware-software co-synthesis using reconfigurable hardware[electronic resource] /Jingzhao Ou, Viktor K. Prasanna. - Boca Raton, Fla :Chapman & Hall/CRC,c2010. - 1 online resource (202 p.) :ill. - Chapman & Hall/CRC computer and information science series. - Chapman & Hall/CRC computer and information science series..

Includes bibliographical references (p. 187-195) and index.

Cover; Title; Copyright; Contents; List of Tables; List of Figures; Acknowledgments; Preface; Chapter 1: Introduction; Chapter 2: Reconfigurable Hardware; Chapter 3: A High-Level Hardware-Software Application Development Framework; Chapter 4: Energy Performance Modeling and Energy Efficient Mapping for a Class of Applications; Chapter 5: High-Level Rapid Energy Estimation and Design Space Exploration; Chapter 6: Hardware-Software Co-Design for Energy Efficient Implementations of Operating Systems; Chapter 7: Concluding Remarks and Future Directions; References; Index;

Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems. Helping overcome these challenges, this book offers solutions for the development of energy efficient applications using FPGAs. It provides a framework for high-level hardware-software application development, describes energy performance modeling for reconfigurable system-on-chip devices, and explores energy efficient designs for various applications. The authors present a two-step rapid energy estimation technique that enables high-level design space exploration and offer a hardware-softw.

ISBN: 9781584887423 (electronic bk.)Subjects--Topical Terms:

2018252
Field programmable gate arrays
--Energy consumption.Index Terms--Genre/Form:

542853
Electronic books.

LC Class. No.: TK7895.G36 / O94 2010eb

Dewey Class. No.: 621.39/5

Energy efficient hardware-software co-synthesis using reconfigurable hardware
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300 $a 1 online resource (202 p.) : $b ill.
490 1 $a Chapman & Hall/CRC computer and information science series
504 $a Includes bibliographical references (p. 187-195) and index.
505 0 $a Cover; Title; Copyright; Contents; List of Tables; List of Figures; Acknowledgments; Preface; Chapter 1: Introduction; Chapter 2: Reconfigurable Hardware; Chapter 3: A High-Level Hardware-Software Application Development Framework; Chapter 4: Energy Performance Modeling and Energy Efficient Mapping for a Class of Applications; Chapter 5: High-Level Rapid Energy Estimation and Design Space Exploration; Chapter 6: Hardware-Software Co-Design for Energy Efficient Implementations of Operating Systems; Chapter 7: Concluding Remarks and Future Directions; References; Index;
520 $a Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems. Helping overcome these challenges, this book offers solutions for the development of energy efficient applications using FPGAs. It provides a framework for high-level hardware-software application development, describes energy performance modeling for reconfigurable system-on-chip devices, and explores energy efficient designs for various applications. The authors present a two-step rapid energy estimation technique that enables high-level design space exploration and offer a hardware-softw.
588 $a Description based on print version record.
650 0 $a Field programmable gate arrays $x Energy consumption. $3 2018252
650 0 $a Field programmable gate arrays $x Design and construction. $3 750060
650 0 $a Adaptive computing systems $x Energy consumption. $3 2018253
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700 1 $a Prasanna Kumar, V. K. $3 653287
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