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Tolerating processor-memory performa...

Lai, Shih-Chang.

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Tolerating processor-memory performance gap.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Tolerating processor-memory performance gap./
Author:	Lai, Shih-Chang.
Description:	94 p.
Notes:	Source: Dissertation Abstracts International, Volume: 63-11, Section: B, page: 5410.
Contained By:	Dissertation Abstracts International63-11B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3069922
ISBN:	0493895574

Tolerating processor-memory performance gap.
Lai, Shih-Chang.

Tolerating processor-memory performance gap. - 94 p.

Source: Dissertation Abstracts International, Volume: 63-11, Section: B, page: 5410.

Thesis (Ph.D.)--Oregon State University, 2003.

While the performance gap between microprocessors and main memory is ever increasing each year, cache memory has been a bridge to alleviate this discrepancy. In this thesis proposal, we introduce three techniques to tolerate this processor and memory speed imbalance. First, we propose the bloom filter scheme to identify which load operant could cause cache miss. Second, we explore a new fault-tolerant microarchitecture to detect transient error occurs. Third, we proposed a novel hardware-only mechanism to solve pointer-chasing problem in Link-list Data Structure application. The simulation shows that the bloom filter may filter out 99% of cache miss. The new fault-tolerant microarchitecture reduce the penalty caused by detecting instruction error about 1.8&sim;13%. The hardware-only data prefetch mechanism accurate predict over 80% of irregular address pattern and improve the performance by 7%.

ISBN: 0493895574Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Tolerating processor-memory performance gap.
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100 1 $a Lai, Shih-Chang. $3 1942973
245 1 0 $a Tolerating processor-memory performance gap.
300 $a 94 p.
500 $a Source: Dissertation Abstracts International, Volume: 63-11, Section: B, page: 5410.
500 $a Adviser: Shih-Lien Lu.
502 $a Thesis (Ph.D.)--Oregon State University, 2003.
520 $a While the performance gap between microprocessors and main memory is ever increasing each year, cache memory has been a bridge to alleviate this discrepancy. In this thesis proposal, we introduce three techniques to tolerate this processor and memory speed imbalance. First, we propose the bloom filter scheme to identify which load operant could cause cache miss. Second, we explore a new fault-tolerant microarchitecture to detect transient error occurs. Third, we proposed a novel hardware-only mechanism to solve pointer-chasing problem in Link-list Data Structure application. The simulation shows that the bloom filter may filter out 99% of cache miss. The new fault-tolerant microarchitecture reduce the penalty caused by detecting instruction error about 1.8&sim;13%. The hardware-only data prefetch mechanism accurate predict over 80% of irregular address pattern and improve the performance by 7%.
590 $a School code: 0172.
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Computer Science. $3 626642
690 $a 0544
690 $a 0984
710 2 0 $a Oregon State University. $3 625720
773 0 $t Dissertation Abstracts International $g 63-11B.
790 1 0 $a Lu, Shih-Lien, $e advisor
790 $a 0172
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3069922