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Piezoresistive behavior of MOSFETs a...

Bradley, Arthur Thomas.

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Piezoresistive behavior of MOSFETs and MOS circuits.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Piezoresistive behavior of MOSFETs and MOS circuits./
作者:	Bradley, Arthur Thomas.
面頁冊數:	285 p.
附註:	Source: Dissertation Abstracts International, Volume: 60-07, Section: B, page: 3443.
Contained By:	Dissertation Abstracts International60-07B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=9939609
ISBN:	0599409231

Piezoresistive behavior of MOSFETs and MOS circuits.
Bradley, Arthur Thomas.

Piezoresistive behavior of MOSFETs and MOS circuits. - 285 p.

Source: Dissertation Abstracts International, Volume: 60-07, Section: B, page: 3443.

Thesis (Ph.D.)--Auburn University, 1999.

This dissertation focuses on the piezoresistive response of MOS devices on (100) silicon. It is meant to supplement existing piezoresistive knowledge, by focusing on three specific areas of investigation. The first is a detailed investigation into the FET channel-length dependence of piezoresistive response. Following the FET discussion, a comparison of the piezoresistive response of a wide variety of device types contained on a common test die is given. Arrays of sensors are then presented that illustrate the usefulness of FET sensors in characterizing stress contours induced by packaging steps.

ISBN: 0599409231Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Piezoresistive behavior of MOSFETs and MOS circuits.
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100 1 $a Bradley, Arthur Thomas. $3 1942963
245 1 0 $a Piezoresistive behavior of MOSFETs and MOS circuits.
300 $a 285 p.
500 $a Source: Dissertation Abstracts International, Volume: 60-07, Section: B, page: 3443.
500 $a Directors: Richard C. Jaegar; Jeffrey C. Suhling.
502 $a Thesis (Ph.D.)--Auburn University, 1999.
520 $a This dissertation focuses on the piezoresistive response of MOS devices on (100) silicon. It is meant to supplement existing piezoresistive knowledge, by focusing on three specific areas of investigation. The first is a detailed investigation into the FET channel-length dependence of piezoresistive response. Following the FET discussion, a comparison of the piezoresistive response of a wide variety of device types contained on a common test die is given. Arrays of sensors are then presented that illustrate the usefulness of FET sensors in characterizing stress contours induced by packaging steps.
520 $a In Chapter 1, the fundamentals of piezoresistance theory are presented beginning with a qualitative discussion that introduces the reader to the solid-state physics of the piezoresistance phenomena in silicon. Topics include energy-band diagrams, constant energy ellipsoids, and changes in effective mass. Derivations are presented for key piezoresistance equations used throughout the dissertation. The chapter concludes with a review of field-effect transistors, including regions of operation, fundamental equations, and an examination of how the general piezoresistance equations developed using traditional resistors can be applied to FETs.
520 $a Chapter 2 investigates the dependence of FET stress sensitivity on device channel length. A thorough investigation is presented that consists of an analysis of sets of devices from three independent sources (Texas Instruments, Lucent Technologies, and IBM). Each of three sets of transistors contains an assortment of devices that range from very short (0.3 μm–0.5 μm) to much longer channel lengths (i.e. 5 μm–15 μm). From the three sets, a clear conclusion as to the channel-length sensitivity issue is drawn.
520 $a Test chips containing arrays of the differential FET stress sensors are detailed in Chapter 3. Individual sensors are constructed of both NMOS and PMOS differential pairs on (100) silicon, permitting the extraction of the in-plane shear stress and the in-plane normal stress difference respectively. The test chip designs, extracted stress components, and comparison between measured and predicted encapsulation results are presented.
520 $a Chapter 4 presents an empirical comparison of piezoresistive sensitivities from a variety of devices contained on a common test die. The die was fabricated by IBM using a 0.25 μm SiGe commercial process and contains an assortment of test structures including n- and p-type resistors, PFET and NFET devices, van der Pauw structures, inversion layer van der Pauw devices, and vertical NPN bipolar junction transistors.
590 $a School code: 0012.
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Engineering, Packaging. $3 1025152
690 $a 0544
690 $a 0549
710 2 0 $a Auburn University. $3 1020457
773 0 $t Dissertation Abstracts International $g 60-07B.
790 1 0 $a Jaegar, Richard C., $e advisor
790 1 0 $a Suhling, Jeffrey C., $e advisor
790 $a 0012
791 $a Ph.D.
792 $a 1999
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=9939609