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The dynamic simultaneous multithread...

Ortiz-Arroyo, Daniel.

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The dynamic simultaneous multithreaded processor.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	The dynamic simultaneous multithreaded processor./
作者:	Ortiz-Arroyo, Daniel.
面頁冊數:	103 p.
附註:	Source: Dissertation Abstracts International, Volume: 64-04, Section: B, page: 1850.
Contained By:	Dissertation Abstracts International64-04B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3080133

The dynamic simultaneous multithreaded processor.
Ortiz-Arroyo, Daniel.

The dynamic simultaneous multithreaded processor. - 103 p.

Source: Dissertation Abstracts International, Volume: 64-04, Section: B, page: 1850.

Thesis (Ph.D.)--Oregon State University, 2003.

This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (<italic>TLP</italic>) and instruction-level-parallelism (ILP) on a <italic> Simultaneous Multithreading</italic> (<italic>SMT</italic>) architecture.Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

The dynamic simultaneous multithreaded processor.
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100 1 $a Ortiz-Arroyo, Daniel. $3 927881
245 1 0 $a The dynamic simultaneous multithreaded processor.
300 $a 103 p.
500 $a Source: Dissertation Abstracts International, Volume: 64-04, Section: B, page: 1850.
500 $a Adviser: Ben (Il-Beom) Lee.
502 $a Thesis (Ph.D.)--Oregon State University, 2003.
520 $a This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (<italic>TLP</italic>) and instruction-level-parallelism (ILP) on a <italic> Simultaneous Multithreading</italic> (<italic>SMT</italic>) architecture.
520 $a First, the <italic>hybrid multithreaded execution</italic> model is discussed. This model combines software-controlled multithreading with hardware support for efficient context switching and thread scheduling. A thread scheduling technique called <italic>set scheduling</italic> is introduced and its impact on the overall performance is described. An analytical model of the hybrid multithreaded execution is developed and validated by simulation. Through stochastic simulation, we find that the application of the hybrid multithreaded execution model results in higher processor utilization than traditional software-controlled multithreading.
520 $a Next, in the main part of this dissertation, a new architecture is proposed: the <italic>Dynamic Simultaneous Multithreading</italic> (DSMT) processor. In this architecture, multiple threads are identified and created speculatively at runtime without compiler help. Subsequently, a SMT processor core executes those threads. The performance of a DSMT processor was evaluated with a new execution-driven simulator developed specifically for the purpose. Our experimental results based on simulation show that DSMT architecture has very good potential to improve SMT processor's performance when there is only a single task available for execution.
590 $a School code: 0172.
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Computer Science. $3 626642
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710 2 0 $a Oregon State University. $3 625720
773 0 $t Dissertation Abstracts International $g 64-04B.
790 1 0 $a Lee, Ben (Il-Beom), $e advisor
790 $a 0172
791 $a Ph.D.
792 $a 2003
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